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authorSrinivas Kandagatla <srinivas.kandagatla@st.com>2013-06-25 07:15:10 -0400
committerOlof Johansson <olof@lixom.net>2013-06-25 16:26:47 -0400
commit65ebcc1158891c8c0abef726d59a7840454ad25d (patch)
tree9907cd1af2d7f679f2b6a5a1192b2ff5df7f11c9 /arch/arm/boot
parent317ddd256b9c24b0d78fa8018f80f1e495481a10 (diff)
ARM: sti: Add STiH415 SOC support
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/st-pincfg.h71
-rw-r--r--arch/arm/boot/dts/stih415-clock.dtsi38
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi268
-rw-r--r--arch/arm/boot/dts/stih415.dtsi87
-rw-r--r--arch/arm/boot/dts/stih41x.dtsi38
5 files changed, 502 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 000000000000..8c45d85ac13e
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
1#ifndef _ST_PINCFG_H_
2#define _ST_PINCFG_H_
3
4/* Alternate functions */
5#define ALT1 1
6#define ALT2 2
7#define ALT3 3
8#define ALT4 4
9#define ALT5 5
10#define ALT6 6
11#define ALT7 7
12
13/* Output enable */
14#define OE (1 << 27)
15/* Pull Up */
16#define PU (1 << 26)
17/* Open Drain */
18#define OD (1 << 26)
19#define RT (1 << 23)
20#define INVERTCLK (1 << 22)
21#define CLKNOTDATA (1 << 21)
22#define DOUBLE_EDGE (1 << 20)
23#define CLK_A (0 << 18)
24#define CLK_B (1 << 18)
25#define CLK_C (2 << 18)
26#define CLK_D (3 << 18)
27
28/* User-frendly defines for Pin Direction */
29 /* oe = 0, pu = 0, od = 0 */
30#define IN (0)
31 /* oe = 0, pu = 1, od = 0 */
32#define IN_PU (PU)
33 /* oe = 1, pu = 0, od = 0 */
34#define OUT (OE)
35 /* oe = 1, pu = 0, od = 1 */
36#define BIDIR (OE | OD)
37 /* oe = 1, pu = 1, od = 1 */
38#define BIDIR_PU (OE | PU | OD)
39
40/* RETIME_TYPE */
41/*
42 * B Mode
43 * Bypass retime with optional delay parameter
44 */
45#define BYPASS (0)
46/*
47 * R0, R1, R0D, R1D modes
48 * single-edge data non inverted clock, retime data with clk
49 */
50#define SE_NICLK_IO (RT)
51/*
52 * RIV0, RIV1, RIV0D, RIV1D modes
53 * single-edge data inverted clock, retime data with clk
54 */
55#define SE_ICLK_IO (RT | INVERTCLK)
56/*
57 * R0E, R1E, R0ED, R1ED modes
58 * double-edge data, retime data with clk
59 */
60#define DE_IO (RT | DOUBLE_EDGE)
61/*
62 * CIV0, CIV1 modes with inverted clock
63 * Retiming the clk pins will park clock & reduce the noise within the core.
64 */
65#define ICLK (RT | CLKNOTDATA | INVERTCLK)
66/*
67 * CLK0, CLK1 modes with non-inverted clock
68 * Retiming the clk pins will park clock & reduce the noise within the core.
69 */
70#define NICLK (RT | CLKNOTDATA)
71#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 000000000000..174c799df741
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/ {
9 clocks {
10 /*
11 * Fixed 30MHz oscillator input to SoC
12 */
13 CLK_SYSIN: CLK_SYSIN {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <30000000>;
17 };
18
19 /*
20 * ARM Peripheral clock for timers
21 */
22 arm_periph_clk: arm_periph_clk {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 };
27
28 /*
29 * Bootloader initialized system infrastructure clock for
30 * serial devices.
31 */
32 CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
33 #clock-cells = <0>;
34 compatible = "fixed-clock";
35 clock-frequency = <100000000>;
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 000000000000..1d322b24d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10/ {
11
12 aliases {
13 gpio0 = &PIO0;
14 gpio1 = &PIO1;
15 gpio2 = &PIO2;
16 gpio3 = &PIO3;
17 gpio4 = &PIO4;
18 gpio5 = &PIO5;
19 gpio6 = &PIO6;
20 gpio7 = &PIO7;
21 gpio8 = &PIO8;
22 gpio9 = &PIO9;
23 gpio10 = &PIO10;
24 gpio11 = &PIO11;
25 gpio12 = &PIO12;
26 gpio13 = &PIO13;
27 gpio14 = &PIO14;
28 gpio15 = &PIO15;
29 gpio16 = &PIO16;
30 gpio17 = &PIO17;
31 gpio18 = &PIO18;
32 gpio19 = &PIO100;
33 gpio20 = &PIO101;
34 gpio21 = &PIO102;
35 gpio22 = &PIO103;
36 gpio23 = &PIO104;
37 gpio24 = &PIO105;
38 gpio25 = &PIO106;
39 gpio26 = &PIO107;
40 };
41
42 soc {
43 pin-controller-sbc {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "st,stih415-sbc-pinctrl";
47 st,syscfg = <&syscfg_sbc>;
48 ranges = <0 0xfe610000 0x5000>;
49
50 PIO0: gpio@fe610000 {
51 gpio-controller;
52 #gpio-cells = <1>;
53 reg = <0 0x100>;
54 st,bank-name = "PIO0";
55 };
56 PIO1: gpio@fe611000 {
57 gpio-controller;
58 #gpio-cells = <1>;
59 reg = <0x1000 0x100>;
60 st,bank-name = "PIO1";
61 };
62 PIO2: gpio@fe612000 {
63 gpio-controller;
64 #gpio-cells = <1>;
65 reg = <0x2000 0x100>;
66 st,bank-name = "PIO2";
67 };
68 PIO3: gpio@fe613000 {
69 gpio-controller;
70 #gpio-cells = <1>;
71 reg = <0x3000 0x100>;
72 st,bank-name = "PIO3";
73 };
74 PIO4: gpio@fe614000 {
75 gpio-controller;
76 #gpio-cells = <1>;
77 reg = <0x4000 0x100>;
78 st,bank-name = "PIO4";
79 };
80
81 sbc_serial1 {
82 pinctrl_sbc_serial1:sbc_serial1 {
83 st,pins {
84 tx = <&PIO2 6 ALT3 OUT>;
85 rx = <&PIO2 7 ALT3 IN>;
86 };
87 };
88 };
89 };
90
91 pin-controller-front {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "st,stih415-front-pinctrl";
95 st,syscfg = <&syscfg_front>;
96 ranges = <0 0xfee00000 0x8000>;
97
98 PIO5: gpio@fee00000 {
99 gpio-controller;
100 #gpio-cells = <1>;
101 reg = <0 0x100>;
102 st,bank-name = "PIO5";
103 };
104 PIO6: gpio@fee01000 {
105 gpio-controller;
106 #gpio-cells = <1>;
107 reg = <0x1000 0x100>;
108 st,bank-name = "PIO6";
109 };
110 PIO7: gpio@fee02000 {
111 gpio-controller;
112 #gpio-cells = <1>;
113 reg = <0x2000 0x100>;
114 st,bank-name = "PIO7";
115 };
116 PIO8: gpio@fee03000 {
117 gpio-controller;
118 #gpio-cells = <1>;
119 reg = <0x3000 0x100>;
120 st,bank-name = "PIO8";
121 };
122 PIO9: gpio@fee04000 {
123 gpio-controller;
124 #gpio-cells = <1>;
125 reg = <0x4000 0x100>;
126 st,bank-name = "PIO9";
127 };
128 PIO10: gpio@fee05000 {
129 gpio-controller;
130 #gpio-cells = <1>;
131 reg = <0x5000 0x100>;
132 st,bank-name = "PIO10";
133 };
134 PIO11: gpio@fee06000 {
135 gpio-controller;
136 #gpio-cells = <1>;
137 reg = <0x6000 0x100>;
138 st,bank-name = "PIO11";
139 };
140 PIO12: gpio@fee07000 {
141 gpio-controller;
142 #gpio-cells = <1>;
143 reg = <0x7000 0x100>;
144 st,bank-name = "PIO12";
145 };
146 };
147
148 pin-controller-rear {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "st,stih415-rear-pinctrl";
152 st,syscfg = <&syscfg_rear>;
153 ranges = <0 0xfe820000 0x8000>;
154
155 PIO13: gpio@fe820000 {
156 gpio-controller;
157 #gpio-cells = <1>;
158 reg = <0 0x100>;
159 st,bank-name = "PIO13";
160 };
161 PIO14: gpio@fe821000 {
162 gpio-controller;
163 #gpio-cells = <1>;
164 reg = <0x1000 0x100>;
165 st,bank-name = "PIO14";
166 };
167 PIO15: gpio@fe822000 {
168 gpio-controller;
169 #gpio-cells = <1>;
170 reg = <0x2000 0x100>;
171 st,bank-name = "PIO15";
172 };
173 PIO16: gpio@fe823000 {
174 gpio-controller;
175 #gpio-cells = <1>;
176 reg = <0x3000 0x100>;
177 st,bank-name = "PIO16";
178 };
179 PIO17: gpio@fe824000 {
180 gpio-controller;
181 #gpio-cells = <1>;
182 reg = <0x4000 0x100>;
183 st,bank-name = "PIO17";
184 };
185 PIO18: gpio@fe825000 {
186 gpio-controller;
187 #gpio-cells = <1>;
188 reg = <0x5000 0x100>;
189 st,bank-name = "PIO18";
190 };
191
192 serial2 {
193 pinctrl_serial2: serial2-0 {
194 st,pins {
195 tx = <&PIO17 4 ALT2 OUT>;
196 rx = <&PIO17 5 ALT2 IN>;
197 };
198 };
199 };
200 };
201
202 pin-controller-left {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "st,stih415-left-pinctrl";
206 st,syscfg = <&syscfg_left>;
207 ranges = <0 0xfd6b0000 0x3000>;
208
209 PIO100: gpio@fd6b0000 {
210 gpio-controller;
211 #gpio-cells = <1>;
212 reg = <0 0x100>;
213 st,bank-name = "PIO100";
214 };
215 PIO101: gpio@fd6b1000 {
216 gpio-controller;
217 #gpio-cells = <1>;
218 reg = <0x1000 0x100>;
219 st,bank-name = "PIO101";
220 };
221 PIO102: gpio@fd6b2000 {
222 gpio-controller;
223 #gpio-cells = <1>;
224 reg = <0x2000 0x100>;
225 st,bank-name = "PIO102";
226 };
227 };
228
229 pin-controller-right {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 compatible = "st,stih415-right-pinctrl";
233 st,syscfg = <&syscfg_right>;
234 ranges = <0 0xfd330000 0x5000>;
235
236 PIO103: gpio@fd330000 {
237 gpio-controller;
238 #gpio-cells = <1>;
239 reg = <0 0x100>;
240 st,bank-name = "PIO103";
241 };
242 PIO104: gpio@fd331000 {
243 gpio-controller;
244 #gpio-cells = <1>;
245 reg = <0x1000 0x100>;
246 st,bank-name = "PIO104";
247 };
248 PIO105: gpio@fd332000 {
249 gpio-controller;
250 #gpio-cells = <1>;
251 reg = <0x2000 0x100>;
252 st,bank-name = "PIO105";
253 };
254 PIO106: gpio@fd333000 {
255 gpio-controller;
256 #gpio-cells = <1>;
257 reg = <0x3000 0x100>;
258 st,bank-name = "PIO106";
259 };
260 PIO107: gpio@fd334000 {
261 gpio-controller;
262 #gpio-cells = <1>;
263 reg = <0x4000 0x100>;
264 st,bank-name = "PIO107";
265 };
266 };
267 };
268};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 000000000000..74ab8ded4b49
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih41x.dtsi"
10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi"
12/ {
13
14 L2: cache-controller {
15 compatible = "arm,pl310-cache";
16 reg = <0xfffe2000 0x1000>;
17 arm,data-latency = <3 2 2>;
18 arm,tag-latency = <1 1 1>;
19 cache-unified;
20 cache-level = <2>;
21 };
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 interrupt-parent = <&intc>;
27 ranges;
28 compatible = "simple-bus";
29
30 syscfg_sbc: sbc-syscfg@fe600000{
31 compatible = "st,stih415-sbc-syscfg", "syscon";
32 reg = <0xfe600000 0xb4>;
33 };
34
35 syscfg_front: front-syscfg@fee10000{
36 compatible = "st,stih415-front-syscfg", "syscon";
37 reg = <0xfee10000 0x194>;
38 };
39
40 syscfg_rear: rear-syscfg@fe830000{
41 compatible = "st,stih415-rear-syscfg", "syscon";
42 reg = <0xfe830000 0x190>;
43 };
44
45 /* MPE syscfgs */
46 syscfg_left: left-syscfg@fd690000{
47 compatible = "st,stih415-left-syscfg", "syscon";
48 reg = <0xfd690000 0x78>;
49 };
50
51 syscfg_right: right-syscfg@fd320000{
52 compatible = "st,stih415-right-syscfg", "syscon";
53 reg = <0xfd320000 0x180>;
54 };
55
56 syscfg_system: system-syscfg@fdde0000 {
57 compatible = "st,stih415-system-syscfg", "syscon";
58 reg = <0xfdde0000 0x15c>;
59 };
60
61 syscfg_lpm: lpm-syscfg@fe4b5100{
62 compatible = "st,stih415-lpm-syscfg", "syscon";
63 reg = <0xfe4b5100 0x08>;
64 };
65
66 serial2: serial@fed32000 {
67 compatible = "st,asc";
68 status = "disabled";
69 reg = <0xfed32000 0x2c>;
70 interrupts = <0 197 0>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_serial2>;
73 clocks = <&CLKS_ICN_REG_0>;
74 };
75
76 /* SBC comms block ASCs in SASG1 */
77 sbc_serial1: serial@fe531000 {
78 compatible = "st,asc";
79 status = "disabled";
80 reg = <0xfe531000 0x2c>;
81 interrupts = <0 210 0>;
82 clocks = <&CLK_SYSIN>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_sbc_serial1>;
85 };
86 };
87};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 000000000000..7321403cab8a
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,38 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4
5 cpus {
6 #address-cells = <1>;
7 #size-cells = <0>;
8 cpu@0 {
9 compatible = "arm,cortex-a9";
10 reg = <0>;
11 };
12 cpu@1 {
13 compatible = "arm,cortex-a9";
14 reg = <1>;
15 };
16 };
17
18 intc: interrupt-controller@fffe1000 {
19 compatible = "arm,cortex-a9-gic";
20 #interrupt-cells = <3>;
21 interrupt-controller;
22 reg = <0xfffe1000 0x1000>,
23 <0xfffe0100 0x100>;
24 };
25
26 scu@fffe0000 {
27 compatible = "arm,cortex-a9-scu";
28 reg = <0xfffe0000 0x1000>;
29 };
30
31 timer@fffe0200 {
32 interrupt-parent = <&intc>;
33 compatible = "arm,cortex-a9-global-timer";
34 reg = <0xfffe0200 0x100>;
35 interrupts = <1 11 0x04>;
36 clocks = <&arm_periph_clk>;
37 };
38};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 09:28:50 -0500