diff options
| author | Mike Turquette <mturquette@linaro.org> | 2014-06-10 19:53:25 -0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-06-10 19:53:25 -0400 |
| commit | 3f6eec9969d24f91a3909d51e86e007ca5efd4c4 (patch) | |
| tree | bff0f51bab78b18d52cfd57ad7cd8b78ac6a882c /arch/arm/boot | |
| parent | 963649d735c8b6eb0f97e82c54f02426ff3f1f45 (diff) | |
| parent | 7e148070001ae82df08966199580a29b934e3bf3 (diff) | |
Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 | ||||
| -rw-r--r-- | arch/arm/boot/dts/omap54xx-clocks.dtsi | 2 |
2 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c7676871d9c0..b03cfe49d22b 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | clock-frequency = <0>; | 26 | clock-frequency = <0>; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | atlclkin3_ck: atlclkin3_ck { | 29 | atl_clkin3_ck: atl_clkin3_ck { |
| 30 | #clock-cells = <0>; | 30 | #clock-cells = <0>; |
| 31 | compatible = "fixed-clock"; | 31 | compatible = "fixed-clock"; |
| 32 | clock-frequency = <0>; | 32 | clock-frequency = <0>; |
| @@ -277,7 +277,7 @@ | |||
| 277 | 277 | ||
| 278 | dpll_mpu_ck: dpll_mpu_ck { | 278 | dpll_mpu_ck: dpll_mpu_ck { |
| 279 | #clock-cells = <0>; | 279 | #clock-cells = <0>; |
| 280 | compatible = "ti,omap4-dpll-clock"; | 280 | compatible = "ti,omap5-mpu-dpll-clock"; |
| 281 | clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; | 281 | clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; |
| 282 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | 282 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; |
| 283 | }; | 283 | }; |
| @@ -730,7 +730,7 @@ | |||
| 730 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { | 730 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { |
| 731 | #clock-cells = <0>; | 731 | #clock-cells = <0>; |
| 732 | compatible = "ti,mux-clock"; | 732 | compatible = "ti,mux-clock"; |
| 733 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 733 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 734 | ti,bit-shift = <28>; | 734 | ti,bit-shift = <28>; |
| 735 | reg = <0x0550>; | 735 | reg = <0x0550>; |
| 736 | }; | 736 | }; |
| @@ -738,7 +738,7 @@ | |||
| 738 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { | 738 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { |
| 739 | #clock-cells = <0>; | 739 | #clock-cells = <0>; |
| 740 | compatible = "ti,mux-clock"; | 740 | compatible = "ti,mux-clock"; |
| 741 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 741 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 742 | ti,bit-shift = <24>; | 742 | ti,bit-shift = <24>; |
| 743 | reg = <0x0550>; | 743 | reg = <0x0550>; |
| 744 | }; | 744 | }; |
| @@ -1639,7 +1639,7 @@ | |||
| 1639 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { | 1639 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { |
| 1640 | #clock-cells = <0>; | 1640 | #clock-cells = <0>; |
| 1641 | compatible = "ti,mux-clock"; | 1641 | compatible = "ti,mux-clock"; |
| 1642 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1642 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1643 | ti,bit-shift = <28>; | 1643 | ti,bit-shift = <28>; |
| 1644 | reg = <0x1860>; | 1644 | reg = <0x1860>; |
| 1645 | }; | 1645 | }; |
| @@ -1647,7 +1647,7 @@ | |||
| 1647 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { | 1647 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { |
| 1648 | #clock-cells = <0>; | 1648 | #clock-cells = <0>; |
| 1649 | compatible = "ti,mux-clock"; | 1649 | compatible = "ti,mux-clock"; |
| 1650 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1650 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1651 | ti,bit-shift = <24>; | 1651 | ti,bit-shift = <24>; |
| 1652 | reg = <0x1860>; | 1652 | reg = <0x1860>; |
| 1653 | }; | 1653 | }; |
| @@ -1663,7 +1663,7 @@ | |||
| 1663 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { | 1663 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { |
| 1664 | #clock-cells = <0>; | 1664 | #clock-cells = <0>; |
| 1665 | compatible = "ti,mux-clock"; | 1665 | compatible = "ti,mux-clock"; |
| 1666 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1666 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1667 | ti,bit-shift = <24>; | 1667 | ti,bit-shift = <24>; |
| 1668 | reg = <0x1868>; | 1668 | reg = <0x1868>; |
| 1669 | }; | 1669 | }; |
| @@ -1679,7 +1679,7 @@ | |||
| 1679 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { | 1679 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { |
| 1680 | #clock-cells = <0>; | 1680 | #clock-cells = <0>; |
| 1681 | compatible = "ti,mux-clock"; | 1681 | compatible = "ti,mux-clock"; |
| 1682 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1682 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1683 | ti,bit-shift = <24>; | 1683 | ti,bit-shift = <24>; |
| 1684 | reg = <0x1898>; | 1684 | reg = <0x1898>; |
| 1685 | }; | 1685 | }; |
| @@ -1695,7 +1695,7 @@ | |||
| 1695 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { | 1695 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { |
| 1696 | #clock-cells = <0>; | 1696 | #clock-cells = <0>; |
| 1697 | compatible = "ti,mux-clock"; | 1697 | compatible = "ti,mux-clock"; |
| 1698 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1698 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1699 | ti,bit-shift = <24>; | 1699 | ti,bit-shift = <24>; |
| 1700 | reg = <0x1878>; | 1700 | reg = <0x1878>; |
| 1701 | }; | 1701 | }; |
| @@ -1711,7 +1711,7 @@ | |||
| 1711 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { | 1711 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { |
| 1712 | #clock-cells = <0>; | 1712 | #clock-cells = <0>; |
| 1713 | compatible = "ti,mux-clock"; | 1713 | compatible = "ti,mux-clock"; |
| 1714 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1714 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1715 | ti,bit-shift = <24>; | 1715 | ti,bit-shift = <24>; |
| 1716 | reg = <0x1904>; | 1716 | reg = <0x1904>; |
| 1717 | }; | 1717 | }; |
| @@ -1727,7 +1727,7 @@ | |||
| 1727 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { | 1727 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { |
| 1728 | #clock-cells = <0>; | 1728 | #clock-cells = <0>; |
| 1729 | compatible = "ti,mux-clock"; | 1729 | compatible = "ti,mux-clock"; |
| 1730 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1730 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1731 | ti,bit-shift = <24>; | 1731 | ti,bit-shift = <24>; |
| 1732 | reg = <0x1908>; | 1732 | reg = <0x1908>; |
| 1733 | }; | 1733 | }; |
| @@ -1743,7 +1743,7 @@ | |||
| 1743 | mcasp8_ahclk_mux: mcasp8_ahclk_mux { | 1743 | mcasp8_ahclk_mux: mcasp8_ahclk_mux { |
| 1744 | #clock-cells = <0>; | 1744 | #clock-cells = <0>; |
| 1745 | compatible = "ti,mux-clock"; | 1745 | compatible = "ti,mux-clock"; |
| 1746 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1746 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1747 | ti,bit-shift = <22>; | 1747 | ti,bit-shift = <22>; |
| 1748 | reg = <0x1890>; | 1748 | reg = <0x1890>; |
| 1749 | }; | 1749 | }; |
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index aeb142ce8e9d..e67a23b5d788 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi | |||
| @@ -335,7 +335,7 @@ | |||
| 335 | 335 | ||
| 336 | dpll_mpu_ck: dpll_mpu_ck { | 336 | dpll_mpu_ck: dpll_mpu_ck { |
| 337 | #clock-cells = <0>; | 337 | #clock-cells = <0>; |
| 338 | compatible = "ti,omap4-dpll-clock"; | 338 | compatible = "ti,omap5-mpu-dpll-clock"; |
| 339 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; | 339 | clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; |
| 340 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; | 340 | reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; |
| 341 | }; | 341 | }; |