diff options
| author | Alexander Shiyan <shc_work@mail.ru> | 2013-08-14 05:05:51 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 11:30:02 -0400 |
| commit | 35878142294a0b27533194fd7c07a65072ea7bd9 (patch) | |
| tree | 5d79ccee8e49926e18256db96b26616349a667b3 /arch/arm/boot | |
| parent | e3c68c864d71bfed2665a872a229b354c5da7a09 (diff) | |
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
This unmix module/pin definitions and reduce indentation for pin
groups, so makes template a bit cleaner.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx51.dtsi | 616 |
1 files changed, 309 insertions, 307 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index f0b25c91e5eb..6d8f94afab02 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -308,313 +308,6 @@ | |||
| 308 | iomuxc: iomuxc@73fa8000 { | 308 | iomuxc: iomuxc@73fa8000 { |
| 309 | compatible = "fsl,imx51-iomuxc"; | 309 | compatible = "fsl,imx51-iomuxc"; |
| 310 | reg = <0x73fa8000 0x4000>; | 310 | reg = <0x73fa8000 0x4000>; |
| 311 | |||
| 312 | audmux { | ||
| 313 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 314 | fsl,pins = < | ||
| 315 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 316 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 317 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 318 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 319 | >; | ||
| 320 | }; | ||
| 321 | }; | ||
| 322 | |||
| 323 | fec { | ||
| 324 | pinctrl_fec_1: fecgrp-1 { | ||
| 325 | fsl,pins = < | ||
| 326 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | ||
| 327 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | ||
| 328 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | ||
| 329 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | ||
| 330 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | ||
| 331 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | ||
| 332 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | ||
| 333 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | ||
| 334 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | ||
| 335 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | ||
| 336 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | ||
| 337 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | ||
| 338 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | ||
| 339 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | ||
| 340 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | ||
| 341 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | ||
| 342 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | ||
| 343 | >; | ||
| 344 | }; | ||
| 345 | |||
| 346 | pinctrl_fec_2: fecgrp-2 { | ||
| 347 | fsl,pins = < | ||
| 348 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 349 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 350 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 351 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 352 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 353 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 354 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 355 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 356 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 357 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 358 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 359 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 360 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 361 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 362 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 363 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 364 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 365 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 366 | >; | ||
| 367 | }; | ||
| 368 | }; | ||
| 369 | |||
| 370 | ecspi1 { | ||
| 371 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 372 | fsl,pins = < | ||
| 373 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 374 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 375 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 376 | >; | ||
| 377 | }; | ||
| 378 | }; | ||
| 379 | |||
| 380 | ecspi2 { | ||
| 381 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 382 | fsl,pins = < | ||
| 383 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 384 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 385 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 386 | >; | ||
| 387 | }; | ||
| 388 | }; | ||
| 389 | |||
| 390 | esdhc1 { | ||
| 391 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 392 | fsl,pins = < | ||
| 393 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 394 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 395 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 396 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 397 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 398 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 399 | >; | ||
| 400 | }; | ||
| 401 | }; | ||
| 402 | |||
| 403 | esdhc2 { | ||
| 404 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 405 | fsl,pins = < | ||
| 406 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 407 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 408 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 409 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 410 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 411 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 412 | >; | ||
| 413 | }; | ||
| 414 | }; | ||
| 415 | |||
| 416 | i2c2 { | ||
| 417 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 418 | fsl,pins = < | ||
| 419 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | ||
| 420 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | ||
| 421 | >; | ||
| 422 | }; | ||
| 423 | |||
| 424 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 425 | fsl,pins = < | ||
| 426 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 427 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 428 | >; | ||
| 429 | }; | ||
| 430 | }; | ||
| 431 | |||
| 432 | ipu_disp1 { | ||
| 433 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 434 | fsl,pins = < | ||
| 435 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 436 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 437 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 438 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 439 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 440 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 441 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 442 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 443 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 444 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 445 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 446 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 447 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 448 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 449 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 450 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 451 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 452 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 453 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 454 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 455 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 456 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 457 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 458 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 459 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ | ||
| 460 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ | ||
| 461 | >; | ||
| 462 | }; | ||
| 463 | }; | ||
| 464 | |||
| 465 | ipu_disp2 { | ||
| 466 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 467 | fsl,pins = < | ||
| 468 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | ||
| 469 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | ||
| 470 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | ||
| 471 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | ||
| 472 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | ||
| 473 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | ||
| 474 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | ||
| 475 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | ||
| 476 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | ||
| 477 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | ||
| 478 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | ||
| 479 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | ||
| 480 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | ||
| 481 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | ||
| 482 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | ||
| 483 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | ||
| 484 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ | ||
| 485 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ | ||
| 486 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | ||
| 487 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | ||
| 488 | >; | ||
| 489 | }; | ||
| 490 | }; | ||
| 491 | |||
| 492 | kpp { | ||
| 493 | pinctrl_kpp_1: kppgrp-1 { | ||
| 494 | fsl,pins = < | ||
| 495 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | ||
| 496 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | ||
| 497 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | ||
| 498 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | ||
| 499 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | ||
| 500 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | ||
| 501 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | ||
| 502 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | ||
| 503 | >; | ||
| 504 | }; | ||
| 505 | }; | ||
| 506 | |||
| 507 | pata { | ||
| 508 | pinctrl_pata_1: patagrp-1 { | ||
| 509 | fsl,pins = < | ||
| 510 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | ||
| 511 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | ||
| 512 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | ||
| 513 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | ||
| 514 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | ||
| 515 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | ||
| 516 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | ||
| 517 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | ||
| 518 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | ||
| 519 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | ||
| 520 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | ||
| 521 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | ||
| 522 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | ||
| 523 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | ||
| 524 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | ||
| 525 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | ||
| 526 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | ||
| 527 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | ||
| 528 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | ||
| 529 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | ||
| 530 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | ||
| 531 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | ||
| 532 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | ||
| 533 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | ||
| 534 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | ||
| 535 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | ||
| 536 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | ||
| 537 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | ||
| 538 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | ||
| 539 | >; | ||
| 540 | }; | ||
| 541 | }; | ||
| 542 | |||
| 543 | uart1 { | ||
| 544 | pinctrl_uart1_1: uart1grp-1 { | ||
| 545 | fsl,pins = < | ||
| 546 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 547 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 548 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | ||
| 549 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | ||
| 550 | >; | ||
| 551 | }; | ||
| 552 | }; | ||
| 553 | |||
| 554 | uart2 { | ||
| 555 | pinctrl_uart2_1: uart2grp-1 { | ||
| 556 | fsl,pins = < | ||
| 557 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 558 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 559 | >; | ||
| 560 | }; | ||
| 561 | }; | ||
| 562 | |||
| 563 | uart3 { | ||
| 564 | pinctrl_uart3_1: uart3grp-1 { | ||
| 565 | fsl,pins = < | ||
| 566 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | ||
| 567 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | ||
| 568 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | ||
| 569 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | ||
| 570 | >; | ||
| 571 | }; | ||
| 572 | |||
| 573 | pinctrl_uart3_2: uart3grp-2 { | ||
| 574 | fsl,pins = < | ||
| 575 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 576 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 577 | >; | ||
| 578 | }; | ||
| 579 | }; | ||
| 580 | |||
| 581 | usbh1 { | ||
| 582 | pinctrl_usbh1_1: usbh1grp-1 { | ||
| 583 | fsl,pins = < | ||
| 584 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | ||
| 585 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | ||
| 586 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | ||
| 587 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | ||
| 588 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | ||
| 589 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | ||
| 590 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | ||
| 591 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | ||
| 592 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | ||
| 593 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | ||
| 594 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | ||
| 595 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | ||
| 596 | >; | ||
| 597 | }; | ||
| 598 | }; | ||
| 599 | |||
| 600 | usbh2 { | ||
| 601 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 602 | fsl,pins = < | ||
| 603 | MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 | ||
| 604 | MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 | ||
| 605 | MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 | ||
| 606 | MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 | ||
| 607 | MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 | ||
| 608 | MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 | ||
| 609 | MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 | ||
| 610 | MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 | ||
| 611 | MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 | ||
| 612 | MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 | ||
| 613 | MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 | ||
| 614 | MX51_PAD_EIM_A26__USBH2_STP 0x1e5 | ||
| 615 | >; | ||
| 616 | }; | ||
| 617 | }; | ||
| 618 | }; | 311 | }; |
| 619 | 312 | ||
| 620 | pwm1: pwm@73fb4000 { | 313 | pwm1: pwm@73fb4000 { |
| @@ -809,3 +502,312 @@ | |||
| 809 | }; | 502 | }; |
| 810 | }; | 503 | }; |
| 811 | }; | 504 | }; |
| 505 | |||
| 506 | &iomuxc { | ||
| 507 | audmux { | ||
| 508 | pinctrl_audmux_1: audmuxgrp-1 { | ||
| 509 | fsl,pins = < | ||
| 510 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 | ||
| 511 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | ||
| 512 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | ||
| 513 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | ||
| 514 | >; | ||
| 515 | }; | ||
| 516 | }; | ||
| 517 | |||
| 518 | fec { | ||
| 519 | pinctrl_fec_1: fecgrp-1 { | ||
| 520 | fsl,pins = < | ||
| 521 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 | ||
| 522 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | ||
| 523 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | ||
| 524 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | ||
| 525 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | ||
| 526 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | ||
| 527 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | ||
| 528 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | ||
| 529 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | ||
| 530 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | ||
| 531 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | ||
| 532 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | ||
| 533 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | ||
| 534 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | ||
| 535 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | ||
| 536 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | ||
| 537 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | ||
| 538 | >; | ||
| 539 | }; | ||
| 540 | |||
| 541 | pinctrl_fec_2: fecgrp-2 { | ||
| 542 | fsl,pins = < | ||
| 543 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 | ||
| 544 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | ||
| 545 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | ||
| 546 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | ||
| 547 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | ||
| 548 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | ||
| 549 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | ||
| 550 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | ||
| 551 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | ||
| 552 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | ||
| 553 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | ||
| 554 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | ||
| 555 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | ||
| 556 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | ||
| 557 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | ||
| 558 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | ||
| 559 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | ||
| 560 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | ||
| 561 | >; | ||
| 562 | }; | ||
| 563 | }; | ||
| 564 | |||
| 565 | ecspi1 { | ||
| 566 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 567 | fsl,pins = < | ||
| 568 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 | ||
| 569 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | ||
| 570 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | ||
| 571 | >; | ||
| 572 | }; | ||
| 573 | }; | ||
| 574 | |||
| 575 | ecspi2 { | ||
| 576 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 577 | fsl,pins = < | ||
| 578 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | ||
| 579 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | ||
| 580 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | ||
| 581 | >; | ||
| 582 | }; | ||
| 583 | }; | ||
| 584 | |||
| 585 | esdhc1 { | ||
| 586 | pinctrl_esdhc1_1: esdhc1grp-1 { | ||
| 587 | fsl,pins = < | ||
| 588 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 | ||
| 589 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | ||
| 590 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | ||
| 591 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | ||
| 592 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | ||
| 593 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | ||
| 594 | >; | ||
| 595 | }; | ||
| 596 | }; | ||
| 597 | |||
| 598 | esdhc2 { | ||
| 599 | pinctrl_esdhc2_1: esdhc2grp-1 { | ||
| 600 | fsl,pins = < | ||
| 601 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 | ||
| 602 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | ||
| 603 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | ||
| 604 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | ||
| 605 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | ||
| 606 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | ||
| 607 | >; | ||
| 608 | }; | ||
| 609 | }; | ||
| 610 | |||
| 611 | i2c2 { | ||
| 612 | pinctrl_i2c2_1: i2c2grp-1 { | ||
| 613 | fsl,pins = < | ||
| 614 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed | ||
| 615 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | ||
| 616 | >; | ||
| 617 | }; | ||
| 618 | |||
| 619 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 620 | fsl,pins = < | ||
| 621 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | ||
| 622 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | ||
| 623 | >; | ||
| 624 | }; | ||
| 625 | }; | ||
| 626 | |||
| 627 | ipu_disp1 { | ||
| 628 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 629 | fsl,pins = < | ||
| 630 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 | ||
| 631 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | ||
| 632 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | ||
| 633 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | ||
| 634 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | ||
| 635 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | ||
| 636 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | ||
| 637 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | ||
| 638 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | ||
| 639 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | ||
| 640 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | ||
| 641 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | ||
| 642 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | ||
| 643 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | ||
| 644 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | ||
| 645 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | ||
| 646 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | ||
| 647 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | ||
| 648 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | ||
| 649 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | ||
| 650 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | ||
| 651 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | ||
| 652 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | ||
| 653 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | ||
| 654 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ | ||
| 655 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ | ||
| 656 | >; | ||
| 657 | }; | ||
| 658 | }; | ||
| 659 | |||
| 660 | ipu_disp2 { | ||
| 661 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 662 | fsl,pins = < | ||
| 663 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 | ||
| 664 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | ||
| 665 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | ||
| 666 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | ||
| 667 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | ||
| 668 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | ||
| 669 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | ||
| 670 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | ||
| 671 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | ||
| 672 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | ||
| 673 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | ||
| 674 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | ||
| 675 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | ||
| 676 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | ||
| 677 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | ||
| 678 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | ||
| 679 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ | ||
| 680 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ | ||
| 681 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */ | ||
| 682 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */ | ||
| 683 | >; | ||
| 684 | }; | ||
| 685 | }; | ||
| 686 | |||
| 687 | kpp { | ||
| 688 | pinctrl_kpp_1: kppgrp-1 { | ||
| 689 | fsl,pins = < | ||
| 690 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | ||
| 691 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | ||
| 692 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | ||
| 693 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | ||
| 694 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | ||
| 695 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | ||
| 696 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | ||
| 697 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | ||
| 698 | >; | ||
| 699 | }; | ||
| 700 | }; | ||
| 701 | |||
| 702 | pata { | ||
| 703 | pinctrl_pata_1: patagrp-1 { | ||
| 704 | fsl,pins = < | ||
| 705 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | ||
| 706 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | ||
| 707 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | ||
| 708 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | ||
| 709 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | ||
| 710 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | ||
| 711 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | ||
| 712 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | ||
| 713 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | ||
| 714 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | ||
| 715 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | ||
| 716 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | ||
| 717 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | ||
| 718 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | ||
| 719 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | ||
| 720 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | ||
| 721 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | ||
| 722 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | ||
| 723 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | ||
| 724 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | ||
| 725 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | ||
| 726 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | ||
| 727 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | ||
| 728 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | ||
| 729 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | ||
| 730 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | ||
| 731 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | ||
| 732 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | ||
| 733 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | ||
| 734 | >; | ||
| 735 | }; | ||
| 736 | }; | ||
| 737 | |||
| 738 | uart1 { | ||
| 739 | pinctrl_uart1_1: uart1grp-1 { | ||
| 740 | fsl,pins = < | ||
| 741 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | ||
| 742 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | ||
| 743 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | ||
| 744 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | ||
| 745 | >; | ||
| 746 | }; | ||
| 747 | }; | ||
| 748 | |||
| 749 | uart2 { | ||
| 750 | pinctrl_uart2_1: uart2grp-1 { | ||
| 751 | fsl,pins = < | ||
| 752 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | ||
| 753 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | ||
| 754 | >; | ||
| 755 | }; | ||
| 756 | }; | ||
| 757 | |||
| 758 | uart3 { | ||
| 759 | pinctrl_uart3_1: uart3grp-1 { | ||
| 760 | fsl,pins = < | ||
| 761 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 | ||
| 762 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | ||
| 763 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | ||
| 764 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | ||
| 765 | >; | ||
| 766 | }; | ||
| 767 | |||
| 768 | pinctrl_uart3_2: uart3grp-2 { | ||
| 769 | fsl,pins = < | ||
| 770 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | ||
| 771 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | ||
| 772 | >; | ||
| 773 | }; | ||
| 774 | }; | ||
| 775 | |||
| 776 | usbh1 { | ||
| 777 | pinctrl_usbh1_1: usbh1grp-1 { | ||
| 778 | fsl,pins = < | ||
| 779 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | ||
| 780 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | ||
| 781 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | ||
| 782 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | ||
| 783 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | ||
| 784 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | ||
| 785 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | ||
| 786 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | ||
| 787 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | ||
| 788 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | ||
| 789 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | ||
| 790 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | ||
| 791 | >; | ||
| 792 | }; | ||
| 793 | }; | ||
| 794 | |||
| 795 | usbh2 { | ||
| 796 | pinctrl_usbh2_1: usbh2grp-1 { | ||
| 797 | fsl,pins = < | ||
| 798 | MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 | ||
| 799 | MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 | ||
| 800 | MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 | ||
| 801 | MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 | ||
| 802 | MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 | ||
| 803 | MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 | ||
| 804 | MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 | ||
| 805 | MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 | ||
| 806 | MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 | ||
| 807 | MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 | ||
| 808 | MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 | ||
| 809 | MX51_PAD_EIM_A26__USBH2_STP 0x1e5 | ||
| 810 | >; | ||
| 811 | }; | ||
| 812 | }; | ||
| 813 | }; | ||