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authorCatalin Marinas <catalin.marinas@arm.com>2009-05-30 09:00:18 -0400
committerCatalin Marinas <catalin.marinas@arm.com>2009-05-30 09:00:18 -0400
commit26584853a44c58f3d6ac7360d697a2ddcd1a3efa (patch)
treea47156d781c6207d316746a056a81ca82b90d452 /arch/arm/boot
parentee8c9571191e588ede9a220ded807e33c4897d91 (diff)
Add core support for ARMv6/v7 big-endian
Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/Makefile5
-rw-r--r--arch/arm/boot/compressed/head.S6
2 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index fbe5eef1f6c9..ce39dc540085 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -40,7 +40,7 @@ ifeq ($(CONFIG_PXA_SHARPSL),y)
40OBJS += head-sharpsl.o 40OBJS += head-sharpsl.o
41endif 41endif
42 42
43ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) 43ifeq ($(CONFIG_CPU_ENDIAN_BE32),y)
44ifeq ($(CONFIG_CPU_CP15),y) 44ifeq ($(CONFIG_CPU_CP15),y)
45OBJS += big-endian.o 45OBJS += big-endian.o
46else 46else
@@ -78,6 +78,9 @@ EXTRA_AFLAGS := -Wa,-march=all
78# linker symbols. We only define initrd_phys and params_phys if the 78# linker symbols. We only define initrd_phys and params_phys if the
79# machine class defined the corresponding makefile variable. 79# machine class defined the corresponding makefile variable.
80LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) 80LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
81ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
82LDFLAGS_vmlinux += --be8
83endif
81ifneq ($(INITRD_PHYS),) 84ifneq ($(INITRD_PHYS),)
82LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS) 85LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
83endif 86endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b371fba1b954..01d49be3b2ca 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -438,6 +438,9 @@ __armv4_mmu_cache_on:
438 mrc p15, 0, r0, c1, c0, 0 @ read control reg 438 mrc p15, 0, r0, c1, c0, 0 @ read control reg
439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
440 orr r0, r0, #0x0030 440 orr r0, r0, #0x0030
441#ifdef CONFIG_CPU_ENDIAN_BE8
442 orr r0, r0, #1 << 25 @ big-endian page tables
443#endif
441 bl __common_mmu_cache_on 444 bl __common_mmu_cache_on
442 mov r0, #0 445 mov r0, #0
443 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 446 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
@@ -455,6 +458,9 @@ __armv7_mmu_cache_on:
455 mrc p15, 0, r0, c1, c0, 0 @ read control reg 458 mrc p15, 0, r0, c1, c0, 0 @ read control reg
456 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 459 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
457 orr r0, r0, #0x003c @ write buffer 460 orr r0, r0, #0x003c @ write buffer
461#ifdef CONFIG_CPU_ENDIAN_BE8
462 orr r0, r0, #1 << 25 @ big-endian page tables
463#endif
458 orrne r0, r0, #1 @ MMU enabled 464 orrne r0, r0, #1 @ MMU enabled
459 movne r1, #-1 465 movne r1, #-1
460 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 466 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer