aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot
diff options
context:
space:
mode:
authorTero Kristo <t-kristo@ti.com>2015-02-12 04:37:13 -0500
committerTero Kristo <t-kristo@ti.com>2015-03-31 14:26:59 -0400
commitd919501feffa8715147582c3ffce96fad0c7016f (patch)
treec749c1114e3d26c57fce809d06d01ff996a7dd72 /arch/arm/boot
parented8509edddebf27e6e69f10c9c314f31ac4f2831 (diff)
ARM: dts: dra7: add minimal l4 bus layout with control module support
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/dra7.dtsi166
1 files changed, 93 insertions, 73 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43..8e50ca3fc102 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -94,17 +94,101 @@
94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
96 96
97 prm: prm@4ae06000 { 97 l4_cfg: l4@4a000000 {
98 compatible = "ti,dra7-prm"; 98 compatible = "ti,dra7-l4-cfg", "simple-bus";
99 reg = <0x4ae06000 0x3000>; 99 #address-cells = <1>;
100 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 100 #size-cells = <1>;
101 ranges = <0 0x4a000000 0x22c000>;
101 102
102 prm_clocks: clocks { 103 scm: scm@2000 {
104 compatible = "ti,dra7-scm-core", "simple-bus";
105 reg = <0x2000 0x2000>;
103 #address-cells = <1>; 106 #address-cells = <1>;
104 #size-cells = <0>; 107 #size-cells = <1>;
108 ranges = <0 0x2000 0x2000>;
109
110 scm_conf: scm_conf@0 {
111 compatible = "syscon";
112 reg = <0x0 0x1400>;
113 #address-cells = <1>;
114 #size-cells = <1>;
115
116 pbias_regulator: pbias_regulator {
117 compatible = "ti,pbias-omap";
118 reg = <0xe00 0x4>;
119 syscon = <&scm_conf>;
120 pbias_mmc_reg: pbias_mmc_omap5 {
121 regulator-name = "pbias_mmc_omap5";
122 regulator-min-microvolt = <1800000>;
123 regulator-max-microvolt = <3000000>;
124 };
125 };
126 };
127
128 dra7_pmx_core: pinmux@1400 {
129 compatible = "ti,dra7-padconf",
130 "pinctrl-single";
131 reg = <0x1400 0x0464>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 #interrupt-cells = <1>;
135 interrupt-controller;
136 pinctrl-single,register-width = <32>;
137 pinctrl-single,function-mask = <0x3fffffff>;
138 };
139 };
140
141 cm_core_aon: cm_core_aon@5000 {
142 compatible = "ti,dra7-cm-core-aon";
143 reg = <0x5000 0x2000>;
144
145 cm_core_aon_clocks: clocks {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 };
149
150 cm_core_aon_clockdomains: clockdomains {
151 };
152 };
153
154 cm_core: cm_core@8000 {
155 compatible = "ti,dra7-cm-core";
156 reg = <0x8000 0x3000>;
157
158 cm_core_clocks: clocks {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 cm_core_clockdomains: clockdomains {
164 };
105 }; 165 };
166 };
106 167
107 prm_clockdomains: clockdomains { 168 l4_wkup: l4@4ae00000 {
169 compatible = "ti,dra7-l4-wkup", "simple-bus";
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0x4ae00000 0x3f000>;
173
174 counter32k: counter@4000 {
175 compatible = "ti,omap-counter32k";
176 reg = <0x4000 0x40>;
177 ti,hwmods = "counter_32k";
178 };
179
180 prm: prm@6000 {
181 compatible = "ti,dra7-prm";
182 reg = <0x6000 0x3000>;
183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
184
185 prm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 prm_clockdomains: clockdomains {
191 };
108 }; 192 };
109 }; 193 };
110 194
@@ -177,70 +261,6 @@
177 }; 261 };
178 }; 262 };
179 263
180 cm_core_aon: cm_core_aon@4a005000 {
181 compatible = "ti,dra7-cm-core-aon";
182 reg = <0x4a005000 0x2000>;
183
184 cm_core_aon_clocks: clocks {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 cm_core_aon_clockdomains: clockdomains {
190 };
191 };
192
193 cm_core: cm_core@4a008000 {
194 compatible = "ti,dra7-cm-core";
195 reg = <0x4a008000 0x3000>;
196
197 cm_core_clocks: clocks {
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
202 cm_core_clockdomains: clockdomains {
203 };
204 };
205
206 counter32k: counter@4ae04000 {
207 compatible = "ti,omap-counter32k";
208 reg = <0x4ae04000 0x40>;
209 ti,hwmods = "counter_32k";
210 };
211
212 dra7_ctrl_core: ctrl_core@4a002000 {
213 compatible = "syscon";
214 reg = <0x4a002000 0x6d0>;
215 };
216
217 dra7_ctrl_general: tisyscon@4a002e00 {
218 compatible = "syscon";
219 reg = <0x4a002e00 0x7c>;
220 };
221
222 pbias_regulator: pbias_regulator {
223 compatible = "ti,pbias-omap";
224 reg = <0 0x4>;
225 syscon = <&dra7_ctrl_general>;
226 pbias_mmc_reg: pbias_mmc_omap5 {
227 regulator-name = "pbias_mmc_omap5";
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3000000>;
230 };
231 };
232
233 dra7_pmx_core: pinmux@4a003400 {
234 compatible = "ti,dra7-padconf", "pinctrl-single";
235 reg = <0x4a003400 0x0464>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 #interrupt-cells = <1>;
239 interrupt-controller;
240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0x3fffffff>;
242 };
243
244 sdma: dma-controller@4a056000 { 264 sdma: dma-controller@4a056000 {
245 compatible = "ti,omap4430-sdma"; 265 compatible = "ti,omap4430-sdma";
246 reg = <0x4a056000 0x1000>; 266 reg = <0x4a056000 0x1000>;
@@ -1410,7 +1430,7 @@
1410 compatible = "ti,dra7-d_can"; 1430 compatible = "ti,dra7-d_can";
1411 ti,hwmods = "dcan1"; 1431 ti,hwmods = "dcan1";
1412 reg = <0x4ae3c000 0x2000>; 1432 reg = <0x4ae3c000 0x2000>;
1413 syscon-raminit = <&dra7_ctrl_core 0x558 0>; 1433 syscon-raminit = <&scm_conf 0x558 0>;
1414 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1434 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&dcan1_sys_clk_mux>; 1435 clocks = <&dcan1_sys_clk_mux>;
1416 status = "disabled"; 1436 status = "disabled";
@@ -1420,7 +1440,7 @@
1420 compatible = "ti,dra7-d_can"; 1440 compatible = "ti,dra7-d_can";
1421 ti,hwmods = "dcan2"; 1441 ti,hwmods = "dcan2";
1422 reg = <0x48480000 0x2000>; 1442 reg = <0x48480000 0x2000>;
1423 syscon-raminit = <&dra7_ctrl_core 0x558 1>; 1443 syscon-raminit = <&scm_conf 0x558 1>;
1424 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&sys_clkin1>; 1445 clocks = <&sys_clkin1>;
1426 status = "disabled"; 1446 status = "disabled";