Merge tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux

Pull more clock framework changes from Mike Turquette:
 "The second half of the clock framework pull requeust for 3.14 is
  dominated by platform support for Qualcomm's MSM SoCs, DT binding
  updates for TI's OMAP-ish processors and additional support for
  Samsung chips.

  Additionally there are other smaller clock driver changes and several
  last minute fixes.  This pull request also includes the HiSilicon
  support that depends on the already-merged arm-soc pull request"

[ Fix up stupid compile error in the source tree with evil merge  - Grumpy Linus ]

* tag 'clk-for-linus-3.14-part2' of git://git.linaro.org/people/mike.turquette/linux: (49 commits)
  clk: sort Makefile
  clk: sunxi: fix overflow when setting up divided factors
  clk: Export more clk-provider functions
  dt-bindings: qcom: Fix warning with duplicate dt define
  clk: si5351: remove variant from platform_data
  clk: samsung: Remove unneeded semicolon
  clk: qcom: Fix modular build
  ARM: OMAP3: use DT clock init if DT data is available
  ARM: AM33xx: remove old clock data and link in new clock init code
  ARM: AM43xx: Enable clock init
  ARM: OMAP: DRA7: Enable clock init
  ARM: OMAP4: remove old clock data and link in new clock init code
  ARM: OMAP2+: io: use new clock init API
  ARM: OMAP2+: PRM: add support for initializing PRCM clock modules from DT
  ARM: OMAP3: hwmod: initialize clkdm from clkdm_name
  ARM: OMAP: hwmod: fix an incorrect clk type cast with _get_clkdm
  ARM: OMAP2+: clock: use driver API instead of direct memory read/write
  ARM: OMAP2+: clock: add support for indexed memmaps
  ARM: dts: am43xx clock data
  ARM: dts: AM35xx: use DT clock data
  ...

25 files changed, 9486 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 000000000000..9ccfe508dea2
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,664 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0040>;
+        };
+
+        adc_tsc_fck: adc_tsc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan0_fck: dcan0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan1_fck: dcan1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp0_fck: mcasp0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp1_fck: mcasp1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex0_fck: smartreflex0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex1_fck: smartreflex1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sha0_fck: sha0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes0_fck: aes0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        rng_fck: rng_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm0_tbclk: ehrpwm0_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm0_gate_tbclk>;
+        };
+
+        ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm1_tbclk: ehrpwm1_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm1_gate_tbclk>;
+        };
+
+        ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm2_tbclk: ehrpwm2_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm2_gate_tbclk>;
+        };
+};
+&prcm_clocks {
+        clk_32768_ck: clk_32768_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        clk_rc32k_ck: clk_rc32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_24000000_ck: virt_24000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        virt_25000000_ck: virt_25000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        tclkin_ck: tclkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0490>, <0x045c>, <0x0468>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m4_ck: dpll_core_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0480>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m5_ck: dpll_core_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0484>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m6_ck: dpll_core_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x04d8>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0488>, <0x0420>, <0x042c>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a8>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0494>, <0x0434>, <0x0440>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a0>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_ddr_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_disp_ck: dpll_disp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0498>, <0x0448>, <0x0454>;
+        };
+
+        dpll_disp_m2_ck: dpll_disp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_disp_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a4>;
+                ti,index-starts-at-one;
+                ti,set-rate-parent;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x048c>, <0x0470>, <0x049c>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                reg = <0x04ac>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        cefuse_fck: cefuse_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0a20>;
+        };
+
+        clk_24mhz: clk_24mhz {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        clkdiv32k_ck: clkdiv32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&clk_24mhz>;
+                clock-mult = <1>;
+                clock-div = <732>;
+        };
+
+        clkdiv32k_ick: clkdiv32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x014c>;
+        };
+
+        l3_gclk: l3_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pruss_ocp_gclk: pruss_ocp_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+                reg = <0x0530>;
+        };
+
+        mmu_fck: mmu_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0914>;
+        };
+
+        timer1_fck: timer1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+                reg = <0x0528>;
+        };
+
+        timer2_fck: timer2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0508>;
+        };
+
+        timer3_fck: timer3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x050c>;
+        };
+
+        timer4_fck: timer4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0510>;
+        };
+
+        timer5_fck: timer5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0518>;
+        };
+
+        timer6_fck: timer6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x051c>;
+        };
+
+        timer7_fck: timer7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0504>;
+        };
+
+        usbotg_fck: usbotg_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x047c>;
+        };
+
+        dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        ieee5000_fck: ieee5000_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x00e4>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+                reg = <0x0538>;
+        };
+
+        l4_rtc_gclk: l4_rtc_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l4hs_gclk: l4hs_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3s_gclk: l3s_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4fw_gclk: l4fw_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4ls_gclk: l4ls_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sysclk_div_ck: sysclk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+                reg = <0x0520>;
+        };
+
+        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+                reg = <0x053c>;
+        };
+
+        gpio0_dbclk: gpio0_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&gpio0_dbclk_mux_ck>;
+                ti,bit-shift = <18>;
+                reg = <0x0408>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00ac>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00b0>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00b4>;
+        };
+
+        lcd_gclk: lcd_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+                reg = <0x0534>;
+                ti,set-rate-parent;
+        };
+
+        mmc_clk: mmc_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x052c>;
+        };
+
+        gfx_fck_div_ck: gfx_fck_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&gfx_fclk_clksel_ck>;
+                reg = <0x052c>;
+                ti,max-div = <2>;
+        };
+
+        sysclkout_pre_ck: sysclkout_pre_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+                reg = <0x0700>;
+        };
+
+        clkout2_div_ck: clkout2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sysclkout_pre_ck>;
+                ti,bit-shift = <3>;
+                ti,max-div = <8>;
+                reg = <0x0700>;
+        };
+
+        dbg_sysclk_ck: dbg_sysclk_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin_ck>;
+                ti,bit-shift = <19>;
+                reg = <0x0414>;
+        };
+
+        dbg_clka_ck: dbg_clka_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_ck>;
+                ti,bit-shift = <30>;
+                reg = <0x0414>;
+        };
+
+        stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0414>;
+        };
+
+        trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0414>;
+        };
+
+        stm_clk_div_ck: stm_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&stm_pmd_clock_mux_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <64>;
+                reg = <0x0414>;
+                ti,index-power-of-two;
+        };
+
+        trace_clk_div_ck: trace_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&trace_pmd_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <64>;
+                reg = <0x0414>;
+                ti,index-power-of-two;
+        };
+
+        clkout2_ck: clkout2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkout2_div_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0700>;
+        };
+};
+
+&prcm_clockdomains {
+        clk_24mhz_clkdm: clk_24mhz_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&clkdiv32k_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f6d8ffe98d0b..6d95d3df33c7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -102,6 +102,32 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                prcm: prcm@44e00000 {
+                        compatible = "ti,am3-prcm";
+                        reg = <0x44e00000 0x4000>;
+
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@44e10000 {
+                        compatible = "ti,am3-scrm";
+                        reg = <0x44e10000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 intc: interrupt-controller@48200000 {
                         compatible = "ti,omap2-intc";
                         interrupt-controller;
@@ -794,3 +820,5 @@
                 };
         };
 };
+
+/include/ "am33xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 2fbe02faa8b1..788391f91684 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -61,3 +61,6 @@
                 };
         };
 };
+
+/include/ "am35xx-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 000000000000..df489d310b50
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,128 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        emac_ick: emac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <1>;
+        };
+
+        emac_fck: emac_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&rmii_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <9>;
+        };
+
+        vpfe_ick: vpfe_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <2>;
+        };
+
+        vpfe_fck: vpfe_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pclk_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <10>;
+        };
+
+        hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <0>;
+        };
+
+        hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <8>;
+        };
+
+        hecc_ck: hecc_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <3>;
+        };
+};
+&cm_clocks {
+        ipss_ick: ipss_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        rmii_ck: rmii_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <50000000>;
+        };
+
+        pclk_ck: pclk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        uart4_ick_am35xx: uart4_ick_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <23>;
+        };
+
+        uart4_fck_am35xx: uart4_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
+                         <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
+                         <&hecc_ck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
+        };
+};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103ab3b1..c6bd4d986c29 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,6 +67,32 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                prcm: prcm@44df0000 {
+                        compatible = "ti,am4-prcm";
+                        reg = <0x44df0000 0x11000>;
+
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@44e10000 {
+                        compatible = "ti,am4-scrm";
+                        reg = <0x44e10000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 edma: edma@49000000 {
                         compatible = "ti,edma3";
                         ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
@@ -665,3 +691,5 @@
                 };
         };
 };
+
+/include/ "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 000000000000..142009cc9332
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0040>;
+        };
+
+        adc_tsc_fck: adc_tsc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan0_fck: dcan0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan1_fck: dcan1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp0_fck: mcasp0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp1_fck: mcasp1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex0_fck: smartreflex0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex1_fck: smartreflex1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sha0_fck: sha0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes0_fck: aes0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+&prcm_clocks {
+        clk_32768_ck: clk_32768_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        clk_rc32k_ck: clk_rc32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_24000000_ck: virt_24000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        virt_25000000_ck: virt_25000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        tclkin_ck: tclkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m4_ck: dpll_core_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d38>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m5_ck: dpll_core_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d3c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m6_ck: dpll_core_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d40>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d70>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2da0>, <0x2da4>, <0x2dac>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2db0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_disp_ck: dpll_disp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+        };
+
+        dpll_disp_m2_ck: dpll_disp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_disp_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e30>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2de0>, <0x2de4>, <0x2dec>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2df0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        clk_24mhz: clk_24mhz {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        clkdiv32k_ck: clkdiv32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&clk_24mhz>;
+                clock-mult = <1>;
+                clock-div = <732>;
+        };
+
+        clkdiv32k_ick: clkdiv32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2a38>;
+        };
+
+        sysclk_div: sysclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pruss_ocp_gclk: pruss_ocp_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+                reg = <0x4248>;
+        };
+
+        clk_32k_tpm_ck: clk_32k_tpm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        timer1_fck: timer1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4200>;
+        };
+
+        timer2_fck: timer2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4204>;
+        };
+
+        timer3_fck: timer3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4208>;
+        };
+
+        timer4_fck: timer4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x420c>;
+        };
+
+        timer5_fck: timer5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4210>;
+        };
+
+        timer6_fck: timer6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4214>;
+        };
+
+        timer7_fck: timer7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4218>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+                reg = <0x422c>;
+        };
+
+        l3_gclk: l3_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sysclk_div>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l4hs_gclk: l4hs_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3s_gclk: l3s_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4ls_gclk: l4ls_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+                reg = <0x4238>;
+        };
+
+        clk_32k_mosc_ck: clk_32k_mosc_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4240>;
+        };
+
+        gpio0_dbclk: gpio0_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&gpio0_dbclk_mux_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2b68>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c78>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c80>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c88>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c90>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c98>;
+        };
+
+        mmc_clk: mmc_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x423c>;
+        };
+
+        gfx_fck_div_ck: gfx_fck_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&gfx_fclk_clksel_ck>;
+                reg = <0x423c>;
+                ti,max-div = <2>;
+        };
+
+        disp_clk: disp_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+                reg = <0x4244>;
+        };
+
+        dpll_extdev_ck: dpll_extdev_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+        };
+
+        dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_extdev_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e70>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mux_synctimer32k_ck: mux_synctimer32k_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+                reg = <0x4230>;
+        };
+
+        synctimer_32kclk: synctimer_32kclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&mux_synctimer32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2a30>;
+        };
+
+        timer8_fck: timer8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x421c>;
+        };
+
+        timer9_fck: timer9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4220>;
+        };
+
+        timer10_fck: timer10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4224>;
+        };
+
+        timer11_fck: timer11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4228>;
+        };
+
+        cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&cpsw_50m_clkdiv>;
+                clock-mult = <1>;
+                clock-div = <10>;
+        };
+
+        dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_ddr_ck>;
+        };
+
+        dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2db8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dll_aging_clk_div: dll_aging_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin_ck>;
+                reg = <0x4250>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        div_core_25m_ck: div_core_25m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sysclk_div>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        func_12m_clk: func_12m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        vtp_clk_div: vtp_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4260>;
+        };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4e8b0a..1fd75aa4639d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -104,6 +104,45 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                prm: prm@4ae06000 {
+                        compatible = "ti,dra7-prm";
+                        reg = <0x4ae06000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core_aon: cm_core_aon@4a005000 {
+                        compatible = "ti,dra7-cm-core-aon";
+                        reg = <0x4a005000 0x2000>;
+
+                        cm_core_aon_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_aon_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core: cm_core@4a008000 {
+                        compatible = "ti,dra7-cm-core";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm_core_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4ae04000 0x40>;
@@ -584,3 +623,5 @@
                 };
         };
 };
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 000000000000..e96da9a898ad
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2015 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+        atl_clkin0_ck: atl_clkin0_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atl_clkin1_ck: atl_clkin1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atl_clkin2_ck: atl_clkin2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atlclkin3_ck: atlclkin3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        hdmi_clkin_ck: hdmi_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        mlb_clkin_ck: mlb_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        mlbp_clkin_ck: mlbp_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <100000000>;
+        };
+
+        ref_clkin0_ck: ref_clkin0_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin1_ck: ref_clkin1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin2_ck: ref_clkin2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin3_ck: ref_clkin3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        rmii_clk_ck: rmii_clk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        sdvenc_clkin_ck: sdvenc_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_20000000_ck: virt_20000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <20000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        sys_clkin2: sys_clkin2 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <22579200>;
+        };
+
+        usb_otg_clkin_ck: usb_otg_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video1_clkin_ck: video1_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video1_m2_clkin_ck: video1_m2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video2_clkin_ck: video2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video2_m2_clkin_ck: video2_m2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        dpll_abe_m2_ck: dpll_abe_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dclk_div: mpu_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_mpu_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_dsp_ck: dpll_dsp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+                reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+        };
+
+        dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0244>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_m2_ck: dpll_iva_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dclk: iva_dclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_iva_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_gpu_ck: dpll_gpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+        };
+
+        dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02e8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0220>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_ck: dpll_gmac_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
+        };
+
+        dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        video2_dclk_div: video2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_m2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_dclk_div: video1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_m2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdmi_dclk_div: hdmi_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_eve_ck: dpll_eve_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+                reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
+        };
+
+        dpll_eve_m2_ck: dpll_eve_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_eve_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0294>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        eve_dclk_div: eve_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_eve_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_ddr_ck>;
+        };
+
+        dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0228>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_dsp_ck>;
+        };
+
+        dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0248>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_gmac_ck>;
+        };
+
+        dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        gmii_m_clk_div: gmii_m_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_gmac_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hdmi_clk2_div: hdmi_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdmi_div_clk: hdmi_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3_iclk_div: l3_iclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_root_clk_div: l4_root_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_clk2_div: video1_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_div_clk: video1_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video2_clk2_div: video2_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video2_div_clk: video2_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ipu1_gfclk_mux: ipu1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0520>;
+        };
+
+        mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x0550>;
+        };
+
+        mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x0550>;
+        };
+
+        timer5_gfclk_mux: timer5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        timer6_gfclk_mux: timer6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0560>;
+        };
+
+        timer7_gfclk_mux: timer7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer8_gfclk_mux: timer8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        uart6_gfclk_mux: uart6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin1: sys_clkin1 {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x0118>;
+        };
+
+        abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+                reg = <0x0114>;
+        };
+
+        abe_dpll_clk_mux: abe_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                reg = <0x011c>;
+                ti,dividers = <8>, <16>;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                reg = <0x0178>;
+                ti,max-div = <2>;
+        };
+
+        abe_giclk_div: abe_giclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&aess_fclk>;
+                reg = <0x0174>;
+                ti,max-div = <2>;
+        };
+
+        abe_lp_clk_div: abe_lp_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                reg = <0x01d8>;
+                ti,dividers = <16>, <32>;
+        };
+
+        abe_sys_clk_div: abe_sys_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                reg = <0x0120>;
+                ti,max-div = <2>;
+        };
+
+        adc_gfclk_mux: adc_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+                reg = <0x01dc>;
+        };
+
+        sys_clk1_dclk_div: sys_clk1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x01c8>;
+                ti,index-power-of-two;
+        };
+
+        sys_clk2_dclk_div: sys_clk2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin2>;
+                ti,max-div = <64>;
+                reg = <0x01cc>;
+                ti,index-power-of-two;
+        };
+
+        per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01bc>;
+                ti,index-power-of-two;
+        };
+
+        dsp_gclk_div: dsp_gclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x018c>;
+                ti,index-power-of-two;
+        };
+
+        gpu_dclk: gpu_dclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gpu_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01a0>;
+                ti,index-power-of-two;
+        };
+
+        emif_phy_dclk_div: emif_phy_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x0190>;
+                ti,index-power-of-two;
+        };
+
+        gmac_250m_dclk_div: gmac_250m_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x019c>;
+                ti,index-power-of-two;
+        };
+
+        l3init_480m_dclk_div: l3init_480m_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01ac>;
+                ti,index-power-of-two;
+        };
+
+        usb_otg_dclk_div: usb_otg_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&usb_otg_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0184>;
+                ti,index-power-of-two;
+        };
+
+        sata_dclk_div: sata_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x01c0>;
+                ti,index-power-of-two;
+        };
+
+        pcie2_dclk_div: pcie2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01b8>;
+                ti,index-power-of-two;
+        };
+
+        pcie_dclk_div: pcie_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&apll_pcie_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01b4>;
+                ti,index-power-of-two;
+        };
+
+        emu_dclk_div: emu_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x0194>;
+                ti,index-power-of-two;
+        };
+
+        secure_32k_dclk_div: secure_32k_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&secure_32k_clk_src_ck>;
+                ti,max-div = <64>;
+                reg = <0x01c4>;
+                ti,index-power-of-two;
+        };
+
+        clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x0158>;
+        };
+
+        clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x015c>;
+        };
+
+        clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x0160>;
+        };
+
+        custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin1>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        eve_clk: eve_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+                reg = <0x0180>;
+        };
+
+        hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01a4>;
+        };
+
+        mlb_clk: mlb_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mlb_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0134>;
+                ti,index-power-of-two;
+        };
+
+        mlbp_clk: mlbp_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mlbp_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0130>;
+                ti,index-power-of-two;
+        };
+
+        per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x0138>;
+                ti,index-power-of-two;
+        };
+
+        timer_sys_clk_div: timer_sys_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                reg = <0x0144>;
+                ti,max-div = <2>;
+        };
+
+        video1_dpll_clk_mux: video1_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01d0>;
+        };
+
+        video2_dpll_clk_mux: video2_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01d4>;
+        };
+
+        wkupaon_iclk_mux: wkupaon_iclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+                reg = <0x0108>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1838>;
+        };
+
+        dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                ti,bit-shift = <24>;
+                reg = <0x1888>;
+        };
+
+        timer1_gfclk_mux: timer1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        uart10_gfclk_mux: uart10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1880>;
+        };
+};
+&cm_core_clocks {
+        dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin1>;
+                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+        };
+
+        dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+                #clock-cells = <0>;
+                reg = <0x021c 0x4>;
+                ti,bit-shift = <7>;
+        };
+
+        apll_pcie_ck: apll_pcie_ck {
+                #clock-cells = <0>;
+                compatible = "ti,dra7-apll-clock";
+                clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+                reg = <0x021c>, <0x0220>;
+        };
+
+        optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+                compatible = "ti,divider-clock";
+                clocks = <&apll_pcie_ck>;
+                #clock-cells = <0>;
+                reg = <0x021c>;
+                ti,bit-shift = <8>;
+                ti,max-div = <2>;
+        };
+
+        optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+                compatible = "ti,gate-clock";
+                clocks = <&apll_pcie_ck>;
+                #clock-cells = <0>;
+                reg = <0x13b0>;
+                ti,bit-shift = <9>;
+        };
+
+        optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+                compatible = "ti,gate-clock";
+                clocks = <&optfclk_pciephy_div>;
+                #clock-cells = <0>;
+                reg = <0x13b0>;
+                ti,bit-shift = <10>;
+        };
+
+        apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        apll_pcie_m2_ck: apll_pcie_m2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+        };
+
+        dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0160>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        func_128m_clk: func_128m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l3init_60m_fclk: l3init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        dss_32khz_clk: dss_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1120>;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1120>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_h12x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1120>;
+        };
+
+        dss_hdmi_clk: dss_hdmi_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&hdmi_dpll_clk_mux>;
+                ti,bit-shift = <10>;
+                reg = <0x1120>;
+        };
+
+        dss_video1_clk: dss_video1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&video1_dpll_clk_mux>;
+                ti,bit-shift = <12>;
+                reg = <0x1120>;
+        };
+
+        dss_video2_clk: dss_video2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&video2_dpll_clk_mux>;
+                ti,bit-shift = <13>;
+                reg = <0x1120>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1760>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1768>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1770>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1778>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1780>;
+        };
+
+        gpio7_dbclk: gpio7_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1810>;
+        };
+
+        gpio8_dbclk: gpio8_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1818>;
+        };
+
+        mmc1_clk32k: mmc1_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1328>;
+        };
+
+        mmc2_clk32k: mmc2_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1330>;
+        };
+
+        mmc3_clk32k: mmc3_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1820>;
+        };
+
+        mmc4_clk32k: mmc4_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1828>;
+        };
+
+        sata_ref_clk: sata_ref_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin1>;
+                ti,bit-shift = <8>;
+                reg = <0x1388>;
+        };
+
+        usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x13f0>;
+        };
+
+        usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x1340>;
+        };
+
+        usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0688>;
+        };
+
+        usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0698>;
+        };
+
+        atl_dpll_clk_mux: atl_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0c00>;
+        };
+
+        atl_gfclk_mux: atl_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+                ti,bit-shift = <26>;
+                reg = <0x0c00>;
+        };
+
+        gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_m2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x13d0>;
+                ti,dividers = <2>;
+        };
+
+        gmac_rft_clk_mux: gmac_rft_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+                ti,bit-shift = <25>;
+                reg = <0x13d0>;
+        };
+
+        gpu_core_gclk_mux: gpu_core_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1220>;
+        };
+
+        gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+                ti,bit-shift = <26>;
+                reg = <0x1220>;
+        };
+
+        l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&wkupaon_iclk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0e50>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x1860>;
+        };
+
+        mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x1860>;
+        };
+
+        mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1860>;
+        };
+
+        mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1868>;
+        };
+
+        mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1868>;
+        };
+
+        mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1898>;
+        };
+
+        mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1898>;
+        };
+
+        mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1878>;
+        };
+
+        mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1878>;
+        };
+
+        mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1904>;
+        };
+
+        mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1904>;
+        };
+
+        mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1908>;
+        };
+
+        mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1908>;
+        };
+
+        mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <22>;
+                reg = <0x1890>;
+        };
+
+        mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <24>;
+                reg = <0x1890>;
+        };
+
+        mmc1_fclk_mux: mmc1_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1328>;
+        };
+
+        mmc1_fclk_div: mmc1_fclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc1_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1328>;
+                ti,index-power-of-two;
+        };
+
+        mmc2_fclk_mux: mmc2_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1330>;
+        };
+
+        mmc2_fclk_div: mmc2_fclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc2_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1330>;
+                ti,index-power-of-two;
+        };
+
+        mmc3_gfclk_mux: mmc3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1820>;
+        };
+
+        mmc3_gfclk_div: mmc3_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc3_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1820>;
+                ti,index-power-of-two;
+        };
+
+        mmc4_gfclk_mux: mmc4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1828>;
+        };
+
+        mmc4_gfclk_div: mmc4_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc4_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1828>;
+                ti,index-power-of-two;
+        };
+
+        qspi_gfclk_mux: qspi_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1838>;
+        };
+
+        qspi_gfclk_div: qspi_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&qspi_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1838>;
+                ti,index-power-of-two;
+        };
+
+        timer10_gfclk_mux: timer10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1728>;
+        };
+
+        timer11_gfclk_mux: timer11_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1730>;
+        };
+
+        timer13_gfclk_mux: timer13_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17c8>;
+        };
+
+        timer14_gfclk_mux: timer14_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17d0>;
+        };
+
+        timer15_gfclk_mux: timer15_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17d8>;
+        };
+
+        timer16_gfclk_mux: timer16_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1830>;
+        };
+
+        timer2_gfclk_mux: timer2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1738>;
+        };
+
+        timer3_gfclk_mux: timer3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1740>;
+        };
+
+        timer4_gfclk_mux: timer4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1748>;
+        };
+
+        timer9_gfclk_mux: timer9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1750>;
+        };
+
+        uart1_gfclk_mux: uart1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        uart2_gfclk_mux: uart2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1848>;
+        };
+
+        uart3_gfclk_mux: uart3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1850>;
+        };
+
+        uart4_gfclk_mux: uart4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1858>;
+        };
+
+        uart5_gfclk_mux: uart5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1870>;
+        };
+
+        uart7_gfclk_mux: uart7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18d0>;
+        };
+
+        uart8_gfclk_mux: uart8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18e0>;
+        };
+
+        uart9_gfclk_mux: uart9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18e8>;
+        };
+
+        vip1_gclk_mux: vip1_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1020>;
+        };
+
+        vip2_gclk_mux: vip2_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1028>;
+        };
+
+        vip3_gclk_mux: vip3_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1030>;
+        };
+};
+
+&cm_core_clockdomains {
+        coreaon_clkdm: coreaon_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 427395c083f5..a5fc83b9c835 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -89,6 +89,45 @@
                         interrupts = <0>;
                 };
 
+                prm: prm@48306000 {
+                        compatible = "ti,omap3-prm";
+                        reg = <0x48306000 0x4000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm: cm@48004000 {
+                        compatible = "ti,omap3-cm";
+                        reg = <0x48004000 0x4000>;
+
+                        cm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@48002000 {
+                        compatible = "ti,omap3-scrm";
+                        reg = <0x48002000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@48320000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x48320000 0x20>;
@@ -632,3 +671,5 @@
                 };
         };
 };
+
+/include/ "omap3xxx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 000000000000..02f6c7fabbec
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,208 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        gfx_l3_ck: gfx_l3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0b10>;
+                ti,bit-shift = <0>;
+        };
+
+        gfx_l3_fck: gfx_l3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_ick>;
+                ti,max-div = <7>;
+                reg = <0x0b40>;
+                ti,index-starts-at-one;
+        };
+
+        gfx_l3_ick: gfx_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&gfx_l3_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gfx_cg1_ck: gfx_cg1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&gfx_l3_fck>;
+                reg = <0x0b00>;
+                ti,bit-shift = <1>;
+        };
+
+        gfx_cg2_ck: gfx_cg2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&gfx_l3_fck>;
+                reg = <0x0b00>;
+                ti,bit-shift = <2>;
+        };
+
+        d2d_26m_fck: d2d_26m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <3>;
+        };
+
+        fshostusb_fck: fshostusb_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <5>;
+        };
+
+        ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0a00>;
+        };
+
+        ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <8>;
+                reg = <0x0a40>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+        };
+
+        ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
+        };
+
+        ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&ssi_ssr_fck_3430es1>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        fac_ick: fac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <8>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ssi_ick_3430es1: ssi_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&ssi_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <0>;
+        };
+
+        usb_l4_gate_ick: usb_l4_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-interface-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <5>;
+                reg = <0x0a10>;
+        };
+
+        usb_l4_div_ick: usb_l4_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <4>;
+                ti,max-div = <1>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        usb_l4_ick: usb_l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+        };
+
+        dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0e00>;
+                ti,set-rate-parent;
+        };
+
+        dss_ick_3430es1: dss_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0e10>;
+                ti,bit-shift = <0>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
+        };
+
+        gfx_3430es1_clkdm: gfx_3430es1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+                         <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
+        };
+
+        d2d_clkdm: d2d_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&d2d_26m_fck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 000000000000..b02017b7630e
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Device Tree Source for OMAP34XX/OMAP36XX clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        security_l4_ick2: security_l4_ick2 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes1_ick: aes1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                ti,bit-shift = <3>;
+                reg = <0x0a14>;
+        };
+
+        rng_ick: rng_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <2>;
+        };
+
+        sha11_ick: sha11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <1>;
+        };
+
+        des1_ick: des1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <0>;
+        };
+
+        cam_mclk: cam_mclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m5x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0f00>;
+                ti,set-rate-parent;
+        };
+
+        cam_ick: cam_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0f10>;
+                ti,bit-shift = <0>;
+        };
+
+        csi2_96m_fck: csi2_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0f00>;
+                ti,bit-shift = <1>;
+        };
+
+        security_l3_ick: security_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pka_ick: pka_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l3_ick>;
+                reg = <0x0a14>;
+                ti,bit-shift = <4>;
+        };
+
+        icr_ick: icr_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <29>;
+        };
+
+        des2_ick: des2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <26>;
+        };
+
+        mspro_ick: mspro_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <23>;
+        };
+
+        mailboxes_ick: mailboxes_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <7>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sr1_fck: sr1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <6>;
+        };
+
+        sr2_fck: sr2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <7>;
+        };
+
+        sr_l4_ick: sr_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll2_fck: dpll2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <19>;
+                ti,max-div = <7>;
+                reg = <0x0040>;
+                ti,index-starts-at-one;
+        };
+
+        dpll2_ck: dpll2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&dpll2_fck>;
+                reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
+                ti,low-power-stop;
+                ti,lock;
+                ti,low-power-bypass;
+        };
+
+        dpll2_m2_ck: dpll2_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0044>;
+                ti,index-starts-at-one;
+        };
+
+        iva2_ck: iva2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&dpll2_m2_ck>;
+                reg = <0x0000>;
+                ti,bit-shift = <0>;
+        };
+
+        modem_fck: modem_fck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <31>;
+        };
+
+        sad2d_ick: sad2d_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <3>;
+        };
+
+        mad2d_ick: mad2d_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0a18>;
+                ti,bit-shift = <3>;
+        };
+
+        mspro_fck: mspro_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+};
+
+&cm_clockdomains {
+        cam_clkdm: cam_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cam_ick>, <&csi2_96m_fck>;
+        };
+
+        iva2_clkdm: iva2_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&iva2_ck>;
+        };
+
+        dpll2_clkdm: dpll2_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll2_ck>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
+        };
+
+        d2d_clkdm: d2d_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
+                         <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
+                         <&mspro_fck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 77d124678c95..2e92360da1f3 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -39,3 +39,7 @@
                 };
         };
 };
+
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 000000000000..af9ae5346bf2
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,242 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        corex2_d3_fck: corex2_d3_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&corex2_fck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        corex2_d5_fck: corex2_d5_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&corex2_fck>;
+                clock-mult = <1>;
+                clock-div = <5>;
+        };
+};
+&cm_clocks {
+        dpll5_ck: dpll5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
+                ti,low-power-stop;
+                ti,lock;
+        };
+
+        dpll5_m2_ck: dpll5_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll5_ck>;
+                ti,max-div = <31>;
+                reg = <0x0d50>;
+                ti,index-starts-at-one;
+        };
+
+        sgx_gate_fck: sgx_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0b00>;
+        };
+
+        core_d3_ck: core_d3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        core_d4_ck: core_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        core_d6_ck: core_d6_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <6>;
+        };
+
+        omap_192m_alwon_fck: omap_192m_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        core_d2_ck: core_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        sgx_mux_fck: sgx_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+                reg = <0x0b40>;
+        };
+
+        sgx_fck: sgx_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
+        };
+
+        sgx_ick: sgx_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0b10>;
+                ti,bit-shift = <0>;
+        };
+
+        cpefuse_fck: cpefuse_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <0>;
+        };
+
+        ts_fck: ts_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_32k_fck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <1>;
+        };
+
+        usbtll_fck: usbtll_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&dpll5_m2_ck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <2>;
+        };
+
+        usbtll_ick: usbtll_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a18>;
+                ti,bit-shift = <2>;
+        };
+
+        mmchs3_ick: mmchs3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <30>;
+        };
+
+        mmchs3_fck: mmchs3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <30>;
+        };
+
+        dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0e00>;
+                ti,set-rate-parent;
+        };
+
+        dss_ick_3430es2: dss_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dss-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0e10>;
+                ti,bit-shift = <0>;
+        };
+
+        usbhost_120m_fck: usbhost_120m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll5_m2_ck>;
+                reg = <0x1400>;
+                ti,bit-shift = <1>;
+        };
+
+        usbhost_48m_fck: usbhost_48m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&omap_48m_fck>;
+                reg = <0x1400>;
+                ti,bit-shift = <0>;
+        };
+
+        usbhost_ick: usbhost_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dss-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x1410>;
+                ti,bit-shift = <0>;
+        };
+};
+
+&cm_clockdomains {
+        dpll5_clkdm: dpll5_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll5_ck>;
+        };
+
+        sgx_clkdm: sgx_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sgx_ick>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+                         <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
+        };
+
+        usbhost_clkdm: usbhost_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
+                         <&usbhost_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 000000000000..2fcf253b677c
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        dpll4_ck: dpll4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-per-j-type-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+        };
+
+        dpll4_m5x2_ck: dpll4_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m5x2_mul_ck>;
+                ti,bit-shift = <0x1e>;
+                reg = <0x0d00>;
+                ti,set-rate-parent;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll3_m3x2_ck: dpll3_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll3_m3x2_mul_ck>;
+                ti,bit-shift = <0xc>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m3x2_ck: dpll4_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m3x2_mul_ck>;
+                ti,bit-shift = <0x1c>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m6x2_ck: dpll4_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m6x2_mul_ck>;
+                ti,bit-shift = <0x1f>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        uart4_fck: uart4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_48m_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <18>;
+        };
+};
+
+&cm_clockdomains {
+        dpll4_clkdm: dpll4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll4_ck>;
+        };
+
+        per_clkdm: per_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+                         <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+                         <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+                         <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+                         <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+                         <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+                         <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>, <&uart4_fck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 000000000000..8ed475dd63c9
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0a00>;
+        };
+
+        ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <8>;
+                reg = <0x0a40>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+        };
+
+        ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
+        };
+
+        ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&ssi_ssr_fck_3430es2>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-hsotgusb-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ssi_ick_3430es2: ssi_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-ssi-interface-clock";
+                clocks = <&ssi_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <0>;
+        };
+
+        usim_gate_fck: usim_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&omap_96m_fck>;
+                ti,bit-shift = <9>;
+                reg = <0x0c00>;
+        };
+
+        sys_d2_ck: sys_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_96m_d2_fck: omap_96m_d2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_96m_d4_fck: omap_96m_d4_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        omap_96m_d8_fck: omap_96m_d8_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        omap_96m_d10_fck: omap_96m_d10_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <10>;
+        };
+
+        dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <20>;
+        };
+
+        usim_mux_fck: usim_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0c40>;
+                ti,index-starts-at-one;
+        };
+
+        usim_fck: usim_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usim_gate_fck>, <&usim_mux_fck>;
+        };
+
+        usim_ick: usim_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <9>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>, <&usim_ick>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&ssi_ick_3430es2>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index b7c7bd96c404..7e8dee9175d6 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -51,3 +51,8 @@
                 };
         };
 };
+
+/include/ "omap36xx-clocks.dtsi"
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 000000000000..cb04d4b37e7f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1660 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        virt_16_8m_ck: virt_16_8m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        osc_sys_ck: osc_sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+                reg = <0x0d40>;
+        };
+
+        sys_ck: sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&osc_sys_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x1270>;
+                ti,index-starts-at-one;
+        };
+
+        sys_clkout1: sys_clkout1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&osc_sys_ck>;
+                reg = <0x0d70>;
+                ti,bit-shift = <7>;
+        };
+
+        dpll3_x2_ck: dpll3_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll3_m2x2_ck: dpll3_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_x2_ck: dpll4_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        corex2_fck: corex2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wkup_l4_ick: wkup_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+&scrm_clocks {
+        mcbsp5_mux_fck: mcbsp5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <4>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp5_fck: mcbsp5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+        };
+
+        mcbsp1_mux_fck: mcbsp1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x0274>;
+        };
+
+        mcbsp1_fck: mcbsp1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+        };
+
+        mcbsp2_mux_fck: mcbsp2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <6>;
+                reg = <0x0274>;
+        };
+
+        mcbsp2_fck: mcbsp2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+        };
+
+        mcbsp3_mux_fck: mcbsp3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp3_fck: mcbsp3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+        };
+
+        mcbsp4_mux_fck: mcbsp4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp4_fck: mcbsp4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+        };
+};
+&cm_clocks {
+        dummy_apb_pclk: dummy_apb_pclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        omap_32k_fck: omap_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12m_ck: virt_12m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13m_ck: virt_13m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_38_4m_ck: virt_38_4m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        dpll4_ck: dpll4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-per-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+        };
+
+        dpll4_m2_ck: dpll4_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <63>;
+                reg = <0x0d48>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        omap_96m_alwon_fck: omap_96m_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll3_ck: dpll3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-core-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
+        };
+
+        dpll3_m3_ck: dpll3_m3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll3_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <31>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll3_m3x2_ck: dpll3_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll3_m3x2_mul_ck>;
+                ti,bit-shift = <0xc>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        emu_core_alwon_ck: emu_core_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sys_altclk: sys_altclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        mcbsp_clks: mcbsp_clks {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        dpll3_m2_ck: dpll3_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll3_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <31>;
+                reg = <0x0d40>;
+                ti,index-starts-at-one;
+        };
+
+        core_ck: core_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll1_fck: dpll1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <19>;
+                ti,max-div = <7>;
+                reg = <0x0940>;
+                ti,index-starts-at-one;
+        };
+
+        dpll1_ck: dpll1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&dpll1_fck>;
+                reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
+        };
+
+        dpll1_x2_ck: dpll1_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll1_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll1_x2m2_ck: dpll1_x2m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll1_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0944>;
+                ti,index-starts-at-one;
+        };
+
+        cm_96m_fck: cm_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_alwon_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        omap_96m_fck: omap_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&cm_96m_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0d40>;
+        };
+
+        dpll4_m3_ck: dpll4_m3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <32>;
+                reg = <0x0e40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m3x2_ck: dpll4_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m3x2_mul_ck>;
+                ti,bit-shift = <0x1c>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        omap_54m_fck: omap_54m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+                ti,bit-shift = <5>;
+                reg = <0x0d40>;
+        };
+
+        cm_96m_d2_fck: cm_96m_d2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&cm_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_48m_fck: omap_48m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+                ti,bit-shift = <3>;
+                reg = <0x0d40>;
+        };
+
+        omap_12m_fck: omap_12m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll4_m4_ck: dpll4_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <32>;
+                reg = <0x0e40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m4_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m4x2_ck: dpll4_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m4x2_mul_ck>;
+                ti,bit-shift = <0x1d>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m5_ck: dpll4_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <63>;
+                reg = <0x0f40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m5_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m5x2_ck: dpll4_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m5x2_mul_ck>;
+                ti,bit-shift = <0x1e>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m6_ck: dpll4_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <63>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m6_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m6x2_ck: dpll4_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m6x2_mul_ck>;
+                ti,bit-shift = <0x1f>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        emu_per_alwon_ck: emu_per_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m6x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        clkout2_src_gate_ck: clkout2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0d70>;
+        };
+
+        clkout2_src_mux_ck: clkout2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+                reg = <0x0d70>;
+        };
+
+        clkout2_src_ck: clkout2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
+        };
+
+        sys_clkout2: sys_clkout2 {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&clkout2_src_ck>;
+                ti,bit-shift = <3>;
+                ti,max-div = <64>;
+                reg = <0x0d70>;
+                ti,index-power-of-two;
+        };
+
+        mpu_ck: mpu_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll1_x2m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        arm_fck: arm_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mpu_ck>;
+                reg = <0x0924>;
+                ti,max-div = <2>;
+        };
+
+        emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&mpu_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3_ick: l3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,max-div = <3>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        l4_ick: l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_ick>;
+                ti,bit-shift = <2>;
+                ti,max-div = <3>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        rm_ick: rm_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <1>;
+                ti,max-div = <3>;
+                reg = <0x0c40>;
+                ti,index-starts-at-one;
+        };
+
+        gpt10_gate_fck: gpt10_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x0a00>;
+        };
+
+        gpt10_mux_fck: gpt10_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0a40>;
+        };
+
+        gpt10_fck: gpt10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+        };
+
+        gpt11_gate_fck: gpt11_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <12>;
+                reg = <0x0a00>;
+        };
+
+        gpt11_mux_fck: gpt11_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0a40>;
+        };
+
+        gpt11_fck: gpt11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+        };
+
+        core_96m_fck: core_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mmchs2_fck: mmchs2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <25>;
+        };
+
+        mmchs1_fck: mmchs1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <24>;
+        };
+
+        i2c3_fck: i2c3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <17>;
+        };
+
+        i2c2_fck: i2c2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <16>;
+        };
+
+        i2c1_fck: i2c1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <15>;
+        };
+
+        mcbsp5_gate_fck: mcbsp5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <10>;
+                reg = <0x0a00>;
+        };
+
+        mcbsp1_gate_fck: mcbsp1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <9>;
+                reg = <0x0a00>;
+        };
+
+        core_48m_fck: core_48m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcspi4_fck: mcspi4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <21>;
+        };
+
+        mcspi3_fck: mcspi3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <20>;
+        };
+
+        mcspi2_fck: mcspi2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <19>;
+        };
+
+        mcspi1_fck: mcspi1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <18>;
+        };
+
+        uart2_fck: uart2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <14>;
+        };
+
+        uart1_fck: uart1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <13>;
+        };
+
+        core_12m_fck: core_12m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_12m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdq_fck: hdq_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_12m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <22>;
+        };
+
+        core_l3_ick: core_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sdrc_ick: sdrc_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <1>;
+        };
+
+        gpmc_fck: gpmc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        core_l4_ick: core_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mmchs2_ick: mmchs2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <25>;
+        };
+
+        mmchs1_ick: mmchs1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <24>;
+        };
+
+        hdq_ick: hdq_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <22>;
+        };
+
+        mcspi4_ick: mcspi4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <21>;
+        };
+
+        mcspi3_ick: mcspi3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <20>;
+        };
+
+        mcspi2_ick: mcspi2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <19>;
+        };
+
+        mcspi1_ick: mcspi1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <18>;
+        };
+
+        i2c3_ick: i2c3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <17>;
+        };
+
+        i2c2_ick: i2c2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <16>;
+        };
+
+        i2c1_ick: i2c1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <15>;
+        };
+
+        uart2_ick: uart2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <14>;
+        };
+
+        uart1_ick: uart1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <13>;
+        };
+
+        gpt11_ick: gpt11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <12>;
+        };
+
+        gpt10_ick: gpt10_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <11>;
+        };
+
+        mcbsp5_ick: mcbsp5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <10>;
+        };
+
+        mcbsp1_ick: mcbsp1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <9>;
+        };
+
+        omapctrl_ick: omapctrl_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <6>;
+        };
+
+        dss_tv_fck: dss_tv_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_54m_fck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <2>;
+        };
+
+        dss_96m_fck: dss_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_96m_fck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <2>;
+        };
+
+        dss2_alwon_fck: dss2_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <1>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        gpt1_gate_fck: gpt1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0c00>;
+        };
+
+        gpt1_mux_fck: gpt1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                reg = <0x0c40>;
+        };
+
+        gpt1_fck: gpt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+        };
+
+        aes2_ick: aes2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                ti,bit-shift = <28>;
+                reg = <0x0a10>;
+        };
+
+        wkup_32k_fck: wkup_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio1_dbck: gpio1_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&wkup_32k_fck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <3>;
+        };
+
+        sha12_ick: sha12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <27>;
+        };
+
+        wdt2_fck: wdt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&wkup_32k_fck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <5>;
+        };
+
+        wdt2_ick: wdt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <5>;
+        };
+
+        wdt1_ick: wdt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <4>;
+        };
+
+        gpio1_ick: gpio1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <3>;
+        };
+
+        omap_32ksync_ick: omap_32ksync_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <2>;
+        };
+
+        gpt12_ick: gpt12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <1>;
+        };
+
+        gpt1_ick: gpt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <0>;
+        };
+
+        per_96m_fck: per_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_alwon_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        per_48m_fck: per_48m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        uart3_fck: uart3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_48m_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <11>;
+        };
+
+        gpt2_gate_fck: gpt2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x1000>;
+        };
+
+        gpt2_mux_fck: gpt2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                reg = <0x1040>;
+        };
+
+        gpt2_fck: gpt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+        };
+
+        gpt3_gate_fck: gpt3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x1000>;
+        };
+
+        gpt3_mux_fck: gpt3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x1040>;
+        };
+
+        gpt3_fck: gpt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+        };
+
+        gpt4_gate_fck: gpt4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x1000>;
+        };
+
+        gpt4_mux_fck: gpt4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x1040>;
+        };
+
+        gpt4_fck: gpt4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+        };
+
+        gpt5_gate_fck: gpt5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x1000>;
+        };
+
+        gpt5_mux_fck: gpt5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x1040>;
+        };
+
+        gpt5_fck: gpt5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+        };
+
+        gpt6_gate_fck: gpt6_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1000>;
+        };
+
+        gpt6_mux_fck: gpt6_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x1040>;
+        };
+
+        gpt6_fck: gpt6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+        };
+
+        gpt7_gate_fck: gpt7_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1000>;
+        };
+
+        gpt7_mux_fck: gpt7_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x1040>;
+        };
+
+        gpt7_fck: gpt7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+        };
+
+        gpt8_gate_fck: gpt8_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x1000>;
+        };
+
+        gpt8_mux_fck: gpt8_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x1040>;
+        };
+
+        gpt8_fck: gpt8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+        };
+
+        gpt9_gate_fck: gpt9_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1000>;
+        };
+
+        gpt9_mux_fck: gpt9_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1040>;
+        };
+
+        gpt9_fck: gpt9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+        };
+
+        per_32k_alwon_fck: per_32k_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio6_dbck: gpio6_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <17>;
+        };
+
+        gpio5_dbck: gpio5_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <16>;
+        };
+
+        gpio4_dbck: gpio4_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <15>;
+        };
+
+        gpio3_dbck: gpio3_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <14>;
+        };
+
+        gpio2_dbck: gpio2_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <13>;
+        };
+
+        wdt3_fck: wdt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <12>;
+        };
+
+        per_l4_ick: per_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio6_ick: gpio6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <17>;
+        };
+
+        gpio5_ick: gpio5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <16>;
+        };
+
+        gpio4_ick: gpio4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <15>;
+        };
+
+        gpio3_ick: gpio3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <14>;
+        };
+
+        gpio2_ick: gpio2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <13>;
+        };
+
+        wdt3_ick: wdt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <12>;
+        };
+
+        uart3_ick: uart3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <11>;
+        };
+
+        uart4_ick: uart4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <18>;
+        };
+
+        gpt9_ick: gpt9_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <10>;
+        };
+
+        gpt8_ick: gpt8_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <9>;
+        };
+
+        gpt7_ick: gpt7_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <8>;
+        };
+
+        gpt6_ick: gpt6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <7>;
+        };
+
+        gpt5_ick: gpt5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <6>;
+        };
+
+        gpt4_ick: gpt4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <5>;
+        };
+
+        gpt3_ick: gpt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <4>;
+        };
+
+        gpt2_ick: gpt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <3>;
+        };
+
+        mcbsp2_ick: mcbsp2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <0>;
+        };
+
+        mcbsp3_ick: mcbsp3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <1>;
+        };
+
+        mcbsp4_ick: mcbsp4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <2>;
+        };
+
+        mcbsp2_gate_fck: mcbsp2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <0>;
+                reg = <0x1000>;
+        };
+
+        mcbsp3_gate_fck: mcbsp3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <1>;
+                reg = <0x1000>;
+        };
+
+        mcbsp4_gate_fck: mcbsp4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x1000>;
+        };
+
+        emu_src_mux_ck: emu_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+                reg = <0x1140>;
+        };
+
+        emu_src_ck: emu_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&emu_src_mux_ck>;
+        };
+
+        pclk_fck: pclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <7>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        pclkx2_fck: pclkx2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        atclk_fck: atclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <4>;
+                ti,max-div = <3>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        traceclk_src_fck: traceclk_src_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x1140>;
+        };
+
+        traceclk_fck: traceclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&traceclk_src_fck>;
+                ti,bit-shift = <11>;
+                ti,max-div = <7>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        secure_32k_fck: secure_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        gpt12_fck: gpt12_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&secure_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&secure_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>;
+        };
+
+        dpll3_clkdm: dpll3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll3_ck>;
+        };
+
+        dpll1_clkdm: dpll1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll1_ck>;
+        };
+
+        per_clkdm: per_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+                         <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+                         <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+                         <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+                         <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+                         <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+                         <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>;
+        };
+
+        emu_clkdm: emu_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&emu_src_ck>;
+        };
+
+        dpll4_clkdm: dpll4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll4_ck>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index a1e05853afcd..d3f8a6e8ca20 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                cm1: cm1@4a004000 {
+                        compatible = "ti,omap4-cm1";
+                        reg = <0x4a004000 0x2000>;
+
+                        cm1_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm1_clockdomains: clockdomains {
+                        };
+                };
+
+                prm: prm@4a306000 {
+                        compatible = "ti,omap4-prm";
+                        reg = <0x4a306000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm2: cm2@4a008000 {
+                        compatible = "ti,omap4-cm2";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm2_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm2_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@4a30a000 {
+                        compatible = "ti,omap4-scrm";
+                        reg = <0x4a30a000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4a304000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4a304000 0x20>;
@@ -707,3 +759,5 @@
                 };
         };
 };
+
+/include/ "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 000000000000..2bd2166f88d3
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        bandgap_fclk: bandgap_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1888>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index ab607a19a613..8c1cfad30d60 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -44,3 +44,5 @@
                 };
         };
 };
+
+/include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 11566bed0035..6b32f520741a 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -52,3 +52,5 @@
                 };
         };
 };
+
+/include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 000000000000..be033e9803e9
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        div_ts_ck: div_ts_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1888>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        bandgap_ts_fclk: bandgap_ts_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&div_ts_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1888>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 000000000000..c821ff5e9b8d
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1651 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm1_clocks {
+        extalt_clkin_ck: extalt_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <59000000>;
+        };
+
+        pad_clks_src_ck: pad_clks_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        pad_clks_ck: pad_clks_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_src_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0108>;
+        };
+
+        pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        slimbus_src_clk: slimbus_src_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        slimbus_clk: slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_src_clk>;
+                ti,bit-shift = <10>;
+                reg = <0x0108>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        tie_low_clock_ck: tie_low_clock_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp1_ck: xclk60mhsp1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp2_ck: xclk60mhsp2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60motg_ck: xclk60motg_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+                reg = <0x01f0>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x0528>;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x012c>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m6x2_ck: dpll_core_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        ddrphy_ck: ddrphy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_core_m5x2_ck: dpll_core_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        div_core_ck: div_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                reg = <0x0100>;
+                ti,max-div = <2>;
+        };
+
+        div_iva_hs_clk: div_iva_hs_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x01dc>;
+                ti,index-power-of-two;
+        };
+
+        div_mpu_hs_clk: div_mpu_hs_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x019c>;
+                ti,index-power-of-two;
+        };
+
+        dpll_core_m4x2_ck: dpll_core_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0138>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dll_clk_div_ck: dll_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_abe_m2_ck: dpll_abe_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_ck>;
+                ti,max-div = <31>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0134>;
+        };
+
+        dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0134>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
+        };
+
+        dpll_core_m7x2_ck: dpll_core_m7x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+                ti,bit-shift = <23>;
+                reg = <0x01ac>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_x2_ck: dpll_iva_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_iva_ck>;
+        };
+
+        dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        per_hs_clk_div_ck: per_hs_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        l3_div_ck: l3_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&div_core_ck>;
+                ti,bit-shift = <4>;
+                ti,max-div = <2>;
+                reg = <0x0100>;
+        };
+
+        l4_div_ck: l4_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <2>;
+                reg = <0x0100>;
+        };
+
+        lp_clk_div_ck: lp_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        mpu_periphclk: mpu_periphclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_mpu_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        ocp_abe_iclk: ocp_abe_iclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&aess_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x0528>;
+                ti,dividers = <2>, <1>;
+        };
+
+        per_abe_24m_fclk: per_abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dmic_sync_mux_ck: dmic_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0538>;
+        };
+
+        func_dmic_abe_gfclk: func_dmic_abe_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0538>;
+        };
+
+        mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0540>;
+        };
+
+        func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0540>;
+        };
+
+        mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0548>;
+        };
+
+        func_mcbsp1_gfclk: func_mcbsp1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0548>;
+        };
+
+        mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0550>;
+        };
+
+        func_mcbsp2_gfclk: func_mcbsp2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0558>;
+        };
+
+        func_mcbsp3_gfclk: func_mcbsp3_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        slimbus1_fclk_1: slimbus1_fclk_1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_24m_clk>;
+                ti,bit-shift = <9>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_fclk_0: slimbus1_fclk_0 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&abe_24m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_fclk_2: slimbus1_fclk_2 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_clk>;
+                ti,bit-shift = <11>;
+                reg = <0x0560>;
+        };
+
+        timer5_sync_mux: timer5_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer6_sync_mux: timer6_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        timer7_sync_mux: timer7_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0578>;
+        };
+
+        timer8_sync_mux: timer8_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0108>;
+        };
+
+        abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        dbgclk_mux_ck: dbgclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+                reg = <0x0108>;
+        };
+
+        syc_clk_div_ck: syc_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin_ck>;
+                reg = <0x0100>;
+                ti,max-div = <2>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1838>;
+        };
+
+        dmt1_clk_mux: dmt1_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        usim_ck: usim_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1858>;
+                ti,dividers = <14>, <18>;
+        };
+
+        usim_fclk: usim_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&usim_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1858>;
+        };
+
+        pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x1a20>;
+        };
+
+        pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x1a20>;
+        };
+
+        stm_clk_div_ck: stm_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&pmd_stm_clock_mux_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <64>;
+                reg = <0x1a20>;
+                ti,index-power-of-two;
+        };
+
+        trace_clk_div_div_ck: trace_clk_div_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&pmd_trace_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1a20>;
+                ti,dividers = <0>, <1>, <2>, <0>, <4>;
+        };
+
+        trace_clk_div_ck: trace_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&trace_clk_div_div_ck>;
+        };
+};
+
+&prm_clockdomains {
+        emu_sys_clkdm: emu_sys_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&trace_clk_div_ck>;
+        };
+};
+
+&cm2_clocks {
+        per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x014c>;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+                reg = <0x0150>;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0154>;
+        };
+
+        dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
+        };
+
+        dpll_per_m4x2_ck: dpll_per_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m5x2_ck: dpll_per_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m6x2_ck: dpll_per_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0160>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m7x2_ck: dpll_per_m7x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b4>;
+                ti,clock-mult = <1>;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        ducati_clk_mux_ck: ducati_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+                reg = <0x0100>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_24mc_fclk: func_24mc_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <4>, <8>;
+        };
+
+        func_48mc_fclk: func_48mc_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_64m_fclk: func_64m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <2>, <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <2>, <4>;
+        };
+
+        init_60m_fclk: init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        per_abe_nc_fclk: per_abe_nc_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                reg = <0x0108>;
+                ti,max-div = <2>;
+        };
+
+        aes1_fck: aes1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15a0>;
+        };
+
+        aes2_fck: aes2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15a8>;
+        };
+
+        dss_sys_clk: dss_sys_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&syc_clk_div_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1120>;
+        };
+
+        dss_tv_clk: dss_tv_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&extalt_clkin_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1120>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m5x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1120>;
+                ti,set-rate-parent;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1120>;
+        };
+
+        dss_fck: dss_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x1120>;
+        };
+
+        fdif_fck: fdif_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <4>;
+                reg = <0x1028>;
+                ti,index-power-of-two;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1460>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1468>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1470>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1478>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1480>;
+        };
+
+        sgx_clk_mux: sgx_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1220>;
+        };
+
+        hsi_fck: hsi_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <4>;
+                reg = <0x1338>;
+                ti,index-power-of-two;
+        };
+
+        iss_ctrlclk: iss_ctrlclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1020>;
+        };
+
+        mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+                ti,bit-shift = <25>;
+                reg = <0x14e0>;
+        };
+
+        per_mcbsp4_gfclk: per_mcbsp4_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x14e0>;
+        };
+
+        hsmmc1_fclk: hsmmc1_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x1328>;
+        };
+
+        hsmmc2_fclk: hsmmc2_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x1330>;
+        };
+
+        ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x13e0>;
+        };
+
+        sha2md5_fck: sha2md5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15c8>;
+        };
+
+        slimbus2_fclk_1: slimbus2_fclk_1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_abe_24m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1538>;
+        };
+
+        slimbus2_fclk_0: slimbus2_fclk_0 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_24mc_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1538>;
+        };
+
+        slimbus2_slimbus_clk: slimbus2_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_slimbus_core_clks_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1538>;
+        };
+
+        smartreflex_core_fck: smartreflex_core_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0638>;
+        };
+
+        smartreflex_iva_fck: smartreflex_iva_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0630>;
+        };
+
+        smartreflex_mpu_fck: smartreflex_mpu_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0628>;
+        };
+
+        cm2_dm10_mux: cm2_dm10_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1428>;
+        };
+
+        cm2_dm11_mux: cm2_dm11_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1430>;
+        };
+
+        cm2_dm2_mux: cm2_dm2_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1438>;
+        };
+
+        cm2_dm3_mux: cm2_dm3_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1440>;
+        };
+
+        cm2_dm4_mux: cm2_dm4_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1448>;
+        };
+
+        cm2_dm9_mux: cm2_dm9_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1450>;
+        };
+
+        usb_host_fs_fck: usb_host_fs_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <1>;
+                reg = <0x13d0>;
+        };
+
+        utmi_p1_gfclk: utmi_p1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p1_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1358>;
+        };
+
+        utmi_p2_gfclk: utmi_p2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p2_gfclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <11>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <12>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_func48mclk: usb_host_hs_func48mclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <15>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_fck: usb_host_hs_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <1>;
+                reg = <0x1358>;
+        };
+
+        otg_60m_gfclk: otg_60m_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1360>;
+        };
+
+        usb_otg_hs_xclk: usb_otg_hs_xclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&otg_60m_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1360>;
+        };
+
+        usb_otg_hs_ick: usb_otg_hs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x1360>;
+        };
+
+        usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_ick: usb_tll_hs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_div_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x1368>;
+        };
+};
+
+&cm2_clockdomains {
+        l3_init_clkdm: l3_init_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+        };
+};
+
+&scrm_clocks {
+        auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_ck: auxclk0_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+        };
+
+        auxclk0_ck: auxclk0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk0_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0310>;
+        };
+
+        auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_ck: auxclk1_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+        };
+
+        auxclk1_ck: auxclk1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk1_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0314>;
+        };
+
+        auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_ck: auxclk2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+        };
+
+        auxclk2_ck: auxclk2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk2_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0318>;
+        };
+
+        auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_ck: auxclk3_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+        };
+
+        auxclk3_ck: auxclk3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk3_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x031c>;
+        };
+
+        auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_ck: auxclk4_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+        };
+
+        auxclk4_ck: auxclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk4_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0320>;
+        };
+
+        auxclk5_src_gate_ck: auxclk5_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0324>;
+        };
+
+        auxclk5_src_mux_ck: auxclk5_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0324>;
+        };
+
+        auxclk5_src_ck: auxclk5_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
+        };
+
+        auxclk5_ck: auxclk5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk5_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0324>;
+        };
+
+        auxclkreq0_ck: auxclkreq0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0210>;
+        };
+
+        auxclkreq1_ck: auxclkreq1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+
+        auxclkreq2_ck: auxclkreq2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0218>;
+        };
+
+        auxclkreq3_ck: auxclkreq3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+
+        auxclkreq4_ck: auxclkreq4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0220>;
+        };
+
+        auxclkreq5_ck: auxclkreq5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0224>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ab9a21ae82f3..a72813a9663e 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -117,6 +117,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                prm: prm@4ae06000 {
+                        compatible = "ti,omap5-prm";
+                        reg = <0x4ae06000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core_aon: cm_core_aon@4a004000 {
+                        compatible = "ti,omap5-cm-core-aon";
+                        reg = <0x4a004000 0x2000>;
+
+                        cm_core_aon_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_aon_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@4ae0a000 {
+                        compatible = "ti,omap5-scrm";
+                        reg = <0x4ae0a000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core: cm_core@4a008000 {
+                        compatible = "ti,omap5-cm-core";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm_core_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4ae04000 0x40>;
@@ -751,3 +803,5 @@
                 };
         };
 };
+
+/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 000000000000..d487fdab3921
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1399 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+        pad_clks_src_ck: pad_clks_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        pad_clks_ck: pad_clks_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_src_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0108>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        slimbus_src_clk: slimbus_src_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        slimbus_clk: slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_src_clk>;
+                ti,bit-shift = <10>;
+                reg = <0x0108>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        xclk60mhsp1_ck: xclk60mhsp1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp2_ck: xclk60mhsp2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        abe_iclk: abe_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&abe_clk>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        abe_lp_clk_div: abe_lp_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_h21x2_ck: dpll_core_h21x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        c2c_fclk: c2c_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h21x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        c2c_iclk: c2c_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&c2c_fclk>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_core_h11x2_ck: dpll_core_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0138>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0134>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_x2_ck: dpll_iva_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_iva_ck>;
+        };
+
+        dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        l3_iclk_div: l3_iclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpu_l3_iclk: gpu_l3_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_root_clk_div: l4_root_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_clk>;
+                ti,bit-shift = <11>;
+                reg = <0x0560>;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x0528>;
+        };
+
+        dmic_sync_mux_ck: dmic_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0538>;
+        };
+
+        dmic_gfclk: dmic_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0538>;
+        };
+
+        mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0540>;
+        };
+
+        mcasp_gfclk: mcasp_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0540>;
+        };
+
+        mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0548>;
+        };
+
+        mcbsp1_gfclk: mcbsp1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0548>;
+        };
+
+        mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0550>;
+        };
+
+        mcbsp2_gfclk: mcbsp2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0558>;
+        };
+
+        mcbsp3_gfclk: mcbsp3_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        timer5_gfclk_mux: timer5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer6_gfclk_mux: timer6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        timer7_gfclk_mux: timer7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0578>;
+        };
+
+        timer8_gfclk_mux: timer8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin: sys_clkin {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                reg = <0x0108>;
+        };
+
+        abe_dpll_clk_mux: abe_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dss_syc_gfclk_div: dss_syc_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wkupaon_iclk_mux: wkupaon_iclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+                reg = <0x0108>;
+        };
+
+        l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&wkupaon_iclk_mux>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1938>;
+        };
+
+        timer1_gfclk_mux: timer1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1940>;
+        };
+};
+&cm_core_clocks {
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+        };
+
+        dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_unipro1_ck: dpll_unipro1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&sys_clkin>;
+                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+        };
+
+        dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_unipro1_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_unipro1_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_unipro2_ck: dpll_unipro2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&sys_clkin>;
+                reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
+        };
+
+        dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_unipro2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_unipro2_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01d0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        func_128m_clk: func_128m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l3init_60m_fclk: l3init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        dss_32khz_clk: dss_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1420>;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1420>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_h12x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1420>;
+        };
+
+        dss_sys_clk: dss_sys_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dss_syc_gfclk_div>;
+                ti,bit-shift = <10>;
+                reg = <0x1420>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1060>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1068>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1070>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1078>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1080>;
+        };
+
+        gpio7_dbclk: gpio7_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1110>;
+        };
+
+        gpio8_dbclk: gpio8_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1118>;
+        };
+
+        iss_ctrlclk: iss_ctrlclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1320>;
+        };
+
+        lli_txphy_clk: lli_txphy_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_unipro1_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x0f20>;
+        };
+
+        lli_txphy_ls_clk: lli_txphy_ls_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_unipro1_m2_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0f20>;
+        };
+
+        mmc1_32khz_clk: mmc1_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1628>;
+        };
+
+        sata_ref_clk: sata_ref_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin>;
+                ti,bit-shift = <8>;
+                reg = <0x1688>;
+        };
+
+        usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <11>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <12>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <6>;
+                reg = <0x1658>;
+        };
+
+        utmi_p1_gfclk: utmi_p1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p1_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1658>;
+        };
+
+        utmi_p2_gfclk: utmi_p2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p2_gfclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1658>;
+        };
+
+        usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x16f0>;
+        };
+
+        usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1668>;
+        };
+
+        usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1668>;
+        };
+
+        usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1668>;
+        };
+
+        fdif_fclk: fdif_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x1328>;
+        };
+
+        gpu_core_gclk_mux: gpu_core_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1520>;
+        };
+
+        gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1520>;
+        };
+
+        hsi_fclk: hsi_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x1638>;
+        };
+
+        mmc1_fclk_mux: mmc1_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1628>;
+        };
+
+        mmc1_fclk: mmc1_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc1_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <2>;
+                reg = <0x1628>;
+        };
+
+        mmc2_fclk_mux: mmc2_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1630>;
+        };
+
+        mmc2_fclk: mmc2_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc2_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <2>;
+                reg = <0x1630>;
+        };
+
+        timer10_gfclk_mux: timer10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1028>;
+        };
+
+        timer11_gfclk_mux: timer11_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1030>;
+        };
+
+        timer2_gfclk_mux: timer2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1038>;
+        };
+
+        timer3_gfclk_mux: timer3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1040>;
+        };
+
+        timer4_gfclk_mux: timer4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1048>;
+        };
+
+        timer9_gfclk_mux: timer9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1050>;
+        };
+};
+
+&cm_core_clockdomains {
+        l3init_clkdm: l3init_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>;
+        };
+};
+
+&scrm_clocks {
+        auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_ck: auxclk0_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+        };
+
+        auxclk0_ck: auxclk0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk0_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0310>;
+        };
+
+        auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_ck: auxclk1_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+        };
+
+        auxclk1_ck: auxclk1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk1_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0314>;
+        };
+
+        auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_ck: auxclk2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+        };
+
+        auxclk2_ck: auxclk2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk2_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0318>;
+        };
+
+        auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_ck: auxclk3_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+        };
+
+        auxclk3_ck: auxclk3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk3_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x031c>;
+        };
+
+        auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_ck: auxclk4_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+        };
+
+        auxclk4_ck: auxclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk4_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0320>;
+        };
+
+        auxclkreq0_ck: auxclkreq0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0210>;
+        };
+
+        auxclkreq1_ck: auxclkreq1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+
+        auxclkreq2_ck: auxclkreq2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0218>;
+        };
+
+        auxclkreq3_ck: auxclkreq3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+};