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authorStephen Warren <swarren@nvidia.com>2012-05-11 19:03:26 -0400
committerStephen Warren <swarren@nvidia.com>2012-05-14 12:55:15 -0400
commitc04abb3a07b56db4756b6f970609e65a8624b0a3 (patch)
tree8d3290dcd70672b60c1a269e4dd17279eace801c /arch/arm/boot
parent2f32b1faa8c75e2e987c5b714ae25491d8477da5 (diff)
ARM: dt: tegra: sort nodes based on bus order
Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts36
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts96
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts88
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts164
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts60
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts86
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi182
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi178
8 files changed, 445 insertions, 445 deletions
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 653d62891791..3b5cd7b07553 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -138,24 +138,6 @@
138 }; 138 };
139 }; 139 };
140 140
141 sdhci@78000000 {
142 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
143 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
144 power-gpios = <&gpio 31 0>; /* gpio PD7 */
145 };
146
147 sdhci@78000200 {
148 status = "disable";
149 };
150
151 sdhci@78000400 {
152 status = "disable";
153 };
154
155 sdhci@78000600 {
156 support-8bit;
157 };
158
159 ahub { 141 ahub {
160 i2s@70080300 { 142 i2s@70080300 {
161 status = "disable"; 143 status = "disable";
@@ -174,6 +156,24 @@
174 }; 156 };
175 }; 157 };
176 158
159 sdhci@78000000 {
160 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
161 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
162 power-gpios = <&gpio 31 0>; /* gpio PD7 */
163 };
164
165 sdhci@78000200 {
166 status = "disable";
167 };
168
169 sdhci@78000400 {
170 status = "disable";
171 };
172
173 sdhci@78000600 {
174 support-8bit;
175 };
176
177 sound { 177 sound {
178 compatible = "nvidia,tegra-audio-wm8903-cardhu", 178 compatible = "nvidia,tegra-audio-wm8903-cardhu",
179 "nvidia,tegra-audio-wm8903"; 179 "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 759e289e7f87..f18385d36dde 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -234,8 +234,28 @@
234 }; 234 };
235 }; 235 };
236 236
237 pmc { 237 i2s@70002a00 {
238 nvidia,invert-interrupt; 238 status = "disable";
239 };
240
241 serial@70006000 {
242 status = "disable";
243 };
244
245 serial@70006040 {
246 status = "disable";
247 };
248
249 serial@70006200 {
250 status = "disable";
251 };
252
253 serial@70006300 {
254 clock-frequency = <216000000>;
255 };
256
257 serial@70006400 {
258 status = "disable";
239 }; 259 };
240 260
241 i2c@7000c000 { 261 i2c@7000c000 {
@@ -268,52 +288,12 @@
268 clock-frequency = <400000>; 288 clock-frequency = <400000>;
269 }; 289 };
270 290
271 i2s@70002a00 { 291 pmc {
272 status = "disable"; 292 nvidia,invert-interrupt;
273 };
274
275 sound {
276 compatible = "nvidia,tegra-audio-wm8903-harmony",
277 "nvidia,tegra-audio-wm8903";
278 nvidia,model = "NVIDIA Tegra Harmony";
279
280 nvidia,audio-routing =
281 "Headphone Jack", "HPOUTR",
282 "Headphone Jack", "HPOUTL",
283 "Int Spk", "ROP",
284 "Int Spk", "RON",
285 "Int Spk", "LOP",
286 "Int Spk", "LON",
287 "Mic Jack", "MICBIAS",
288 "IN1L", "Mic Jack";
289
290 nvidia,i2s-controller = <&tegra_i2s1>;
291 nvidia,audio-codec = <&wm8903>;
292
293 nvidia,spkr-en-gpios = <&wm8903 2 0>;
294 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
295 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
296 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
297 };
298
299 serial@70006000 {
300 status = "disable";
301 };
302
303 serial@70006040 {
304 status = "disable";
305 };
306
307 serial@70006200 {
308 status = "disable";
309 };
310
311 serial@70006300 {
312 clock-frequency = <216000000>;
313 }; 293 };
314 294
315 serial@70006400 { 295 usb@c5004000 {
316 status = "disable"; 296 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
317 }; 297 };
318 298
319 sdhci@c8000000 { 299 sdhci@c8000000 {
@@ -337,7 +317,27 @@
337 support-8bit; 317 support-8bit;
338 }; 318 };
339 319
340 usb@c5004000 { 320 sound {
341 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 321 compatible = "nvidia,tegra-audio-wm8903-harmony",
322 "nvidia,tegra-audio-wm8903";
323 nvidia,model = "NVIDIA Tegra Harmony";
324
325 nvidia,audio-routing =
326 "Headphone Jack", "HPOUTR",
327 "Headphone Jack", "HPOUTL",
328 "Int Spk", "ROP",
329 "Int Spk", "RON",
330 "Int Spk", "LOP",
331 "Int Spk", "LON",
332 "Mic Jack", "MICBIAS",
333 "IN1L", "Mic Jack";
334
335 nvidia,i2s-controller = <&tegra_i2s1>;
336 nvidia,audio-codec = <&wm8903>;
337
338 nvidia,spkr-en-gpios = <&wm8903 2 0>;
339 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
340 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
341 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
342 }; 342 };
343}; 343};
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index d469322afbb8..b500212cc01c 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -226,6 +226,30 @@
226 }; 226 };
227 }; 227 };
228 228
229 i2s@70002a00 {
230 status = "disable";
231 };
232
233 serial@70006000 {
234 clock-frequency = <216000000>;
235 };
236
237 serial@70006040 {
238 status = "disable";
239 };
240
241 serial@70006200 {
242 clock-frequency = <216000000>;
243 };
244
245 serial@70006300 {
246 status = "disable";
247 };
248
249 serial@70006400 {
250 status = "disable";
251 };
252
229 i2c@7000c000 { 253 i2c@7000c000 {
230 clock-frequency = <400000>; 254 clock-frequency = <400000>;
231 255
@@ -265,48 +289,8 @@
265 }; 289 };
266 }; 290 };
267 291
268 i2s@70002a00 { 292 usb@c5004000 {
269 status = "disable"; 293 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
270 };
271
272 sound {
273 compatible = "nvidia,tegra-audio-alc5632-paz00",
274 "nvidia,tegra-audio-alc5632";
275
276 nvidia,model = "Compal PAZ00";
277
278 nvidia,audio-routing =
279 "Int Spk", "SPKOUT",
280 "Int Spk", "SPKOUTN",
281 "Headset Mic", "MICBIAS1",
282 "MIC1", "Headset Mic",
283 "Headset Stereophone", "HPR",
284 "Headset Stereophone", "HPL",
285 "DMICDAT", "Digital Mic";
286
287 nvidia,audio-codec = <&alc5632>;
288 nvidia,i2s-controller = <&tegra_i2s1>;
289 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
290 };
291
292 serial@70006000 {
293 clock-frequency = <216000000>;
294 };
295
296 serial@70006040 {
297 status = "disable";
298 };
299
300 serial@70006200 {
301 clock-frequency = <216000000>;
302 };
303
304 serial@70006300 {
305 status = "disable";
306 };
307
308 serial@70006400 {
309 status = "disable";
310 }; 294 };
311 295
312 sdhci@c8000000 { 296 sdhci@c8000000 {
@@ -348,7 +332,23 @@
348 }; 332 };
349 }; 333 };
350 334
351 usb@c5004000 { 335 sound {
352 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 336 compatible = "nvidia,tegra-audio-alc5632-paz00",
337 "nvidia,tegra-audio-alc5632";
338
339 nvidia,model = "Compal PAZ00";
340
341 nvidia,audio-routing =
342 "Int Spk", "SPKOUT",
343 "Int Spk", "SPKOUTN",
344 "Headset Mic", "MICBIAS1",
345 "MIC1", "Headset Mic",
346 "Headset Stereophone", "HPR",
347 "Headset Stereophone", "HPL",
348 "DMICDAT", "Digital Mic";
349
350 nvidia,audio-codec = <&alc5632>;
351 nvidia,i2s-controller = <&tegra_i2s1>;
352 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
353 }; 353 };
354}; 354};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index c935a2871846..88f3b8e0c8c0 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -257,6 +257,30 @@
257 }; 257 };
258 }; 258 };
259 259
260 i2s@70002a00 {
261 status = "disable";
262 };
263
264 serial@70006000 {
265 status = "disable";
266 };
267
268 serial@70006040 {
269 status = "disable";
270 };
271
272 serial@70006200 {
273 status = "disable";
274 };
275
276 serial@70006300 {
277 clock-frequency = <216000000>;
278 };
279
280 serial@70006400 {
281 status = "disable";
282 };
283
260 i2c@7000c000 { 284 i2c@7000c000 {
261 clock-frequency = <400000>; 285 clock-frequency = <400000>;
262 286
@@ -321,50 +345,51 @@
321 }; 345 };
322 }; 346 };
323 347
324 i2s@70002a00 { 348 emc {
325 status = "disable"; 349 emc-table@190000 {
326 }; 350 reg = <190000>;
327 351 compatible = "nvidia,tegra20-emc-table";
328 sound { 352 clock-frequency = <190000>;
329 compatible = "nvidia,tegra-audio-wm8903-seaboard", 353 nvidia,emc-registers = <0x0000000c 0x00000026
330 "nvidia,tegra-audio-wm8903"; 354 0x00000009 0x00000003 0x00000004 0x00000004
331 nvidia,model = "NVIDIA Tegra Seaboard"; 355 0x00000002 0x0000000c 0x00000003 0x00000003
332 356 0x00000002 0x00000001 0x00000004 0x00000005
333 nvidia,audio-routing = 357 0x00000004 0x00000009 0x0000000d 0x0000059f
334 "Headphone Jack", "HPOUTR", 358 0x00000000 0x00000003 0x00000003 0x00000003
335 "Headphone Jack", "HPOUTL", 359 0x00000003 0x00000001 0x0000000b 0x000000c8
336 "Int Spk", "ROP", 360 0x00000003 0x00000007 0x00000004 0x0000000f
337 "Int Spk", "RON", 361 0x00000002 0x00000000 0x00000000 0x00000002
338 "Int Spk", "LOP", 362 0x00000000 0x00000000 0x00000083 0xa06204ae
339 "Int Spk", "LON", 363 0x007dc010 0x00000000 0x00000000 0x00000000
340 "Mic Jack", "MICBIAS", 364 0x00000000 0x00000000 0x00000000 0x00000000>;
341 "IN1R", "Mic Jack"; 365 };
342
343 nvidia,i2s-controller = <&tegra_i2s1>;
344 nvidia,audio-codec = <&wm8903>;
345
346 nvidia,spkr-en-gpios = <&wm8903 2 0>;
347 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
348 };
349
350 serial@70006000 {
351 status = "disable";
352 };
353
354 serial@70006040 {
355 status = "disable";
356 };
357 366
358 serial@70006200 { 367 emc-table@380000 {
359 status = "disable"; 368 reg = <380000>;
369 compatible = "nvidia,tegra20-emc-table";
370 clock-frequency = <380000>;
371 nvidia,emc-registers = <0x00000017 0x0000004b
372 0x00000012 0x00000006 0x00000004 0x00000005
373 0x00000003 0x0000000c 0x00000006 0x00000006
374 0x00000003 0x00000001 0x00000004 0x00000005
375 0x00000004 0x00000009 0x0000000d 0x00000b5f
376 0x00000000 0x00000003 0x00000003 0x00000006
377 0x00000006 0x00000001 0x00000011 0x000000c8
378 0x00000003 0x0000000e 0x00000007 0x0000000f
379 0x00000002 0x00000000 0x00000000 0x00000002
380 0x00000000 0x00000000 0x00000083 0xe044048b
381 0x007d8010 0x00000000 0x00000000 0x00000000
382 0x00000000 0x00000000 0x00000000 0x00000000>;
383 };
360 }; 384 };
361 385
362 serial@70006300 { 386 usb@c5000000 {
363 clock-frequency = <216000000>; 387 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
388 dr_mode = "otg";
364 }; 389 };
365 390
366 serial@70006400 { 391 usb@c5004000 {
367 status = "disable"; 392 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
368 }; 393 };
369 394
370 sdhci@c8000000 { 395 sdhci@c8000000 {
@@ -385,11 +410,6 @@
385 support-8bit; 410 support-8bit;
386 }; 411 };
387 412
388 usb@c5000000 {
389 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
390 dr_mode = "otg";
391 };
392
393 gpio-keys { 413 gpio-keys {
394 compatible = "gpio-keys"; 414 compatible = "gpio-keys";
395 415
@@ -410,45 +430,25 @@
410 }; 430 };
411 }; 431 };
412 432
413 emc { 433 sound {
414 emc-table@190000 { 434 compatible = "nvidia,tegra-audio-wm8903-seaboard",
415 reg = <190000>; 435 "nvidia,tegra-audio-wm8903";
416 compatible = "nvidia,tegra20-emc-table"; 436 nvidia,model = "NVIDIA Tegra Seaboard";
417 clock-frequency = <190000>;
418 nvidia,emc-registers = <0x0000000c 0x00000026
419 0x00000009 0x00000003 0x00000004 0x00000004
420 0x00000002 0x0000000c 0x00000003 0x00000003
421 0x00000002 0x00000001 0x00000004 0x00000005
422 0x00000004 0x00000009 0x0000000d 0x0000059f
423 0x00000000 0x00000003 0x00000003 0x00000003
424 0x00000003 0x00000001 0x0000000b 0x000000c8
425 0x00000003 0x00000007 0x00000004 0x0000000f
426 0x00000002 0x00000000 0x00000000 0x00000002
427 0x00000000 0x00000000 0x00000083 0xa06204ae
428 0x007dc010 0x00000000 0x00000000 0x00000000
429 0x00000000 0x00000000 0x00000000 0x00000000>;
430 };
431 437
432 emc-table@380000 { 438 nvidia,audio-routing =
433 reg = <380000>; 439 "Headphone Jack", "HPOUTR",
434 compatible = "nvidia,tegra20-emc-table"; 440 "Headphone Jack", "HPOUTL",
435 clock-frequency = <380000>; 441 "Int Spk", "ROP",
436 nvidia,emc-registers = <0x00000017 0x0000004b 442 "Int Spk", "RON",
437 0x00000012 0x00000006 0x00000004 0x00000005 443 "Int Spk", "LOP",
438 0x00000003 0x0000000c 0x00000006 0x00000006 444 "Int Spk", "LON",
439 0x00000003 0x00000001 0x00000004 0x00000005 445 "Mic Jack", "MICBIAS",
440 0x00000004 0x00000009 0x0000000d 0x00000b5f 446 "IN1R", "Mic Jack";
441 0x00000000 0x00000003 0x00000003 0x00000006
442 0x00000006 0x00000001 0x00000011 0x000000c8
443 0x00000003 0x0000000e 0x00000007 0x0000000f
444 0x00000002 0x00000000 0x00000000 0x00000002
445 0x00000000 0x00000000 0x00000083 0xe044048b
446 0x007d8010 0x00000000 0x00000000 0x00000000
447 0x00000000 0x00000000 0x00000000 0x00000000>;
448 };
449 };
450 447
451 usb@c5004000 { 448 nvidia,i2s-controller = <&tegra_i2s1>;
452 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 449 nvidia,audio-codec = <&wm8903>;
450
451 nvidia,spkr-en-gpios = <&wm8903 2 0>;
452 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
453 }; 453 };
454}; 454};
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index eebcf504d12d..1dea6cc68dde 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -240,6 +240,30 @@
240 }; 240 };
241 }; 241 };
242 242
243 i2s@70002a00 {
244 status = "disable";
245 };
246
247 serial@70006000 {
248 clock-frequency = <216000000>;
249 };
250
251 serial@70006040 {
252 status = "disable";
253 };
254
255 serial@70006200 {
256 status = "disable";
257 };
258
259 serial@70006300 {
260 status = "disable";
261 };
262
263 serial@70006400 {
264 status = "disable";
265 };
266
243 i2c@7000c000 { 267 i2c@7000c000 {
244 clock-frequency = <400000>; 268 clock-frequency = <400000>;
245 }; 269 };
@@ -266,34 +290,8 @@
266 status = "disable"; 290 status = "disable";
267 }; 291 };
268 292
269 i2s@70002a00 { 293 usb@c5004000 {
270 status = "disable"; 294 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
271 };
272
273 sound {
274 compatible = "nvidia,tegra-audio-trimslice";
275 nvidia,i2s-controller = <&tegra_i2s1>;
276 nvidia,audio-codec = <&codec>;
277 };
278
279 serial@70006000 {
280 clock-frequency = <216000000>;
281 };
282
283 serial@70006040 {
284 status = "disable";
285 };
286
287 serial@70006200 {
288 status = "disable";
289 };
290
291 serial@70006300 {
292 status = "disable";
293 };
294
295 serial@70006400 {
296 status = "disable";
297 }; 295 };
298 296
299 sdhci@c8000200 { 297 sdhci@c8000200 {
@@ -309,7 +307,9 @@
309 wp-gpios = <&gpio 122 0>; /* gpio PP2 */ 307 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
310 }; 308 };
311 309
312 usb@c5004000 { 310 sound {
313 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 311 compatible = "nvidia,tegra-audio-trimslice";
312 nvidia,i2s-controller = <&tegra_i2s1>;
313 nvidia,audio-codec = <&codec>;
314 }; 314 };
315}; 315};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index e64318d595d5..6de4c106024f 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -240,6 +240,30 @@
240 }; 240 };
241 }; 241 };
242 242
243 i2s@70002a00 {
244 status = "disable";
245 };
246
247 serial@70006000 {
248 status = "disable";
249 };
250
251 serial@70006040 {
252 status = "disable";
253 };
254
255 serial@70006200 {
256 status = "disable";
257 };
258
259 serial@70006300 {
260 clock-frequency = <216000000>;
261 };
262
263 serial@70006400 {
264 status = "disable";
265 };
266
243 i2c@7000c000 { 267 i2c@7000c000 {
244 clock-frequency = <400000>; 268 clock-frequency = <400000>;
245 269
@@ -278,10 +302,28 @@
278 clock-frequency = <400000>; 302 clock-frequency = <400000>;
279 }; 303 };
280 304
281 i2s@70002a00 { 305 usb@c5004000 {
306 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
307 };
308
309 sdhci@c8000000 {
282 status = "disable"; 310 status = "disable";
283 }; 311 };
284 312
313 sdhci@c8000200 {
314 status = "disable";
315 };
316
317 sdhci@c8000400 {
318 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
319 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
320 power-gpios = <&gpio 70 0>; /* gpio PI6 */
321 };
322
323 sdhci@c8000600 {
324 support-8bit;
325 };
326
285 sound { 327 sound {
286 compatible = "nvidia,tegra-audio-wm8903-ventana", 328 compatible = "nvidia,tegra-audio-wm8903-ventana",
287 "nvidia,tegra-audio-wm8903"; 329 "nvidia,tegra-audio-wm8903";
@@ -305,46 +347,4 @@
305 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ 347 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
306 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 348 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
307 }; 349 };
308
309 serial@70006000 {
310 status = "disable";
311 };
312
313 serial@70006040 {
314 status = "disable";
315 };
316
317 serial@70006200 {
318 status = "disable";
319 };
320
321 serial@70006300 {
322 clock-frequency = <216000000>;
323 };
324
325 serial@70006400 {
326 status = "disable";
327 };
328
329 sdhci@c8000000 {
330 status = "disable";
331 };
332
333 sdhci@c8000200 {
334 status = "disable";
335 };
336
337 sdhci@c8000400 {
338 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
339 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
340 power-gpios = <&gpio 70 0>; /* gpio PI6 */
341 };
342
343 sdhci@c8000600 {
344 support-8bit;
345 };
346
347 usb@c5004000 {
348 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
349 };
350}; 350};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 5f9110af43b1..0e371f92d1d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,11 +4,6 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller { 7 intc: interrupt-controller {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
14 interrupt-controller; 9 interrupt-controller;
@@ -17,12 +12,6 @@
17 0x50040100 0x0100>; 12 0x50040100 0x0100>;
18 }; 13 };
19 14
20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
26 apbdma: dma { 15 apbdma: dma {
27 compatible = "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>; 17 reg = <0x6000a000 0x1200>;
@@ -44,55 +33,9 @@
44 0 119 0x04>; 33 0 119 0x04>;
45 }; 34 };
46 35
47 i2c@7000c000 { 36 ahb {
48 #address-cells = <1>; 37 compatible = "nvidia,tegra20-ahb";
49 #size-cells = <0>; 38 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
50 compatible = "nvidia,tegra20-i2c";
51 reg = <0x7000c000 0x100>;
52 interrupts = <0 38 0x04>;
53 };
54
55 i2c@7000c400 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 compatible = "nvidia,tegra20-i2c";
59 reg = <0x7000c400 0x100>;
60 interrupts = <0 84 0x04>;
61 };
62
63 i2c@7000c500 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 compatible = "nvidia,tegra20-i2c";
67 reg = <0x7000c500 0x100>;
68 interrupts = <0 92 0x04>;
69 };
70
71 i2c@7000d000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 compatible = "nvidia,tegra20-i2c-dvc";
75 reg = <0x7000d000 0x200>;
76 interrupts = <0 53 0x04>;
77 };
78
79 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>;
82 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = <&apbdma 2>;
84 };
85
86 tegra_i2s2: i2s@70002a00 {
87 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>;
89 interrupts = <0 3 0x04>;
90 nvidia,dma-request-selector = <&apbdma 1>;
91 };
92
93 das {
94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>;
96 }; 39 };
97 40
98 gpio: gpio { 41 gpio: gpio {
@@ -119,6 +62,25 @@
119 0x70000868 0xa8>; /* Pad control registers */ 62 0x70000868 0xa8>; /* Pad control registers */
120 }; 63 };
121 64
65 das {
66 compatible = "nvidia,tegra20-das";
67 reg = <0x70000c00 0x80>;
68 };
69
70 tegra_i2s1: i2s@70002800 {
71 compatible = "nvidia,tegra20-i2s";
72 reg = <0x70002800 0x200>;
73 interrupts = <0 13 0x04>;
74 nvidia,dma-request-selector = <&apbdma 2>;
75 };
76
77 tegra_i2s2: i2s@70002a00 {
78 compatible = "nvidia,tegra20-i2s";
79 reg = <0x70002a00 0x200>;
80 interrupts = <0 3 0x04>;
81 nvidia,dma-request-selector = <&apbdma 1>;
82 };
83
122 serial@70006000 { 84 serial@70006000 {
123 compatible = "nvidia,tegra20-uart"; 85 compatible = "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 86 reg = <0x70006000 0x40>;
@@ -154,35 +116,61 @@
154 interrupts = <0 91 0x04>; 116 interrupts = <0 91 0x04>;
155 }; 117 };
156 118
157 emc { 119 i2c@7000c000 {
158 #address-cells = <1>; 120 #address-cells = <1>;
159 #size-cells = <0>; 121 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc"; 122 compatible = "nvidia,tegra20-i2c";
161 reg = <0x7000f400 0x200>; 123 reg = <0x7000c000 0x100>;
124 interrupts = <0 38 0x04>;
162 }; 125 };
163 126
164 sdhci@c8000000 { 127 i2c@7000c400 {
165 compatible = "nvidia,tegra20-sdhci"; 128 #address-cells = <1>;
166 reg = <0xc8000000 0x200>; 129 #size-cells = <0>;
167 interrupts = <0 14 0x04>; 130 compatible = "nvidia,tegra20-i2c";
131 reg = <0x7000c400 0x100>;
132 interrupts = <0 84 0x04>;
168 }; 133 };
169 134
170 sdhci@c8000200 { 135 i2c@7000c500 {
171 compatible = "nvidia,tegra20-sdhci"; 136 #address-cells = <1>;
172 reg = <0xc8000200 0x200>; 137 #size-cells = <0>;
173 interrupts = <0 15 0x04>; 138 compatible = "nvidia,tegra20-i2c";
139 reg = <0x7000c500 0x100>;
140 interrupts = <0 92 0x04>;
174 }; 141 };
175 142
176 sdhci@c8000400 { 143 i2c@7000d000 {
177 compatible = "nvidia,tegra20-sdhci"; 144 #address-cells = <1>;
178 reg = <0xc8000400 0x200>; 145 #size-cells = <0>;
179 interrupts = <0 19 0x04>; 146 compatible = "nvidia,tegra20-i2c-dvc";
147 reg = <0x7000d000 0x200>;
148 interrupts = <0 53 0x04>;
180 }; 149 };
181 150
182 sdhci@c8000600 { 151 pmc {
183 compatible = "nvidia,tegra20-sdhci"; 152 compatible = "nvidia,tegra20-pmc";
184 reg = <0xc8000600 0x200>; 153 reg = <0x7000e400 0x400>;
185 interrupts = <0 31 0x04>; 154 };
155
156 mc {
157 compatible = "nvidia,tegra20-mc";
158 reg = <0x7000f000 0x024
159 0x7000f03c 0x3c4>;
160 interrupts = <0 77 0x04>;
161 };
162
163 gart {
164 compatible = "nvidia,tegra20-gart";
165 reg = <0x7000f024 0x00000018 /* controller registers */
166 0x58000000 0x02000000>; /* GART aperture */
167 };
168
169 emc {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "nvidia,tegra20-emc";
173 reg = <0x7000f400 0x200>;
186 }; 174 };
187 175
188 usb@c5000000 { 176 usb@c5000000 {
@@ -207,21 +195,33 @@
207 phy_type = "utmi"; 195 phy_type = "utmi";
208 }; 196 };
209 197
210 ahb { 198 sdhci@c8000000 {
211 compatible = "nvidia,tegra20-ahb"; 199 compatible = "nvidia,tegra20-sdhci";
212 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 200 reg = <0xc8000000 0x200>;
201 interrupts = <0 14 0x04>;
213 }; 202 };
214 203
215 mc { 204 sdhci@c8000200 {
216 compatible = "nvidia,tegra20-mc"; 205 compatible = "nvidia,tegra20-sdhci";
217 reg = <0x7000f000 0x024 206 reg = <0xc8000200 0x200>;
218 0x7000f03c 0x3c4>; 207 interrupts = <0 15 0x04>;
219 interrupts = <0 77 0x04>;
220 }; 208 };
221 209
222 gart { 210 sdhci@c8000400 {
223 compatible = "nvidia,tegra20-gart"; 211 compatible = "nvidia,tegra20-sdhci";
224 reg = <0x7000f024 0x00000018 /* controller registers */ 212 reg = <0xc8000400 0x200>;
225 0x58000000 0x02000000>; /* GART aperture */ 213 interrupts = <0 19 0x04>;
214 };
215
216 sdhci@c8000600 {
217 compatible = "nvidia,tegra20-sdhci";
218 reg = <0xc8000600 0x200>;
219 interrupts = <0 31 0x04>;
220 };
221
222 pmu {
223 compatible = "arm,cortex-a9-pmu";
224 interrupts = <0 56 0x04
225 0 57 0x04>;
226 }; 226 };
227}; 227};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ea829f5bae01..9fb47adc935d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,11 +4,6 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc {
8 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller { 7 intc: interrupt-controller {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
14 interrupt-controller; 9 interrupt-controller;
@@ -17,14 +12,6 @@
17 0x50040100 0x0100>; 12 0x50040100 0x0100>;
18 }; 13 };
19 14
20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
28 apbdma: dma { 15 apbdma: dma {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>; 17 reg = <0x6000a000 0x1400>;
@@ -62,44 +49,9 @@
62 0 143 0x04>; 49 0 143 0x04>;
63 }; 50 };
64 51
65 i2c@7000c000 { 52 ahb: ahb {
66 #address-cells = <1>; 53 compatible = "nvidia,tegra30-ahb";
67 #size-cells = <0>; 54 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69 reg = <0x7000c000 0x100>;
70 interrupts = <0 38 0x04>;
71 };
72
73 i2c@7000c400 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77 reg = <0x7000c400 0x100>;
78 interrupts = <0 84 0x04>;
79 };
80
81 i2c@7000c500 {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85 reg = <0x7000c500 0x100>;
86 interrupts = <0 92 0x04>;
87 };
88
89 i2c@7000c700 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c700 0x100>;
94 interrupts = <0 120 0x04>;
95 };
96
97 i2c@7000d000 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
101 reg = <0x7000d000 0x100>;
102 interrupts = <0 53 0x04>;
103 }; 55 };
104 56
105 gpio: gpio { 57 gpio: gpio {
@@ -119,6 +71,12 @@
119 interrupt-controller; 71 interrupt-controller;
120 }; 72 };
121 73
74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */
78 };
79
122 serial@70006000 { 80 serial@70006000 {
123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 81 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 82 reg = <0x70006000 0x40>;
@@ -154,34 +112,68 @@
154 interrupts = <0 91 0x04>; 112 interrupts = <0 91 0x04>;
155 }; 113 };
156 114
157 sdhci@78000000 { 115 i2c@7000c000 {
158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 116 #address-cells = <1>;
159 reg = <0x78000000 0x200>; 117 #size-cells = <0>;
160 interrupts = <0 14 0x04>; 118 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
119 reg = <0x7000c000 0x100>;
120 interrupts = <0 38 0x04>;
161 }; 121 };
162 122
163 sdhci@78000200 { 123 i2c@7000c400 {
164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 124 #address-cells = <1>;
165 reg = <0x78000200 0x200>; 125 #size-cells = <0>;
166 interrupts = <0 15 0x04>; 126 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
127 reg = <0x7000c400 0x100>;
128 interrupts = <0 84 0x04>;
167 }; 129 };
168 130
169 sdhci@78000400 { 131 i2c@7000c500 {
170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 132 #address-cells = <1>;
171 reg = <0x78000400 0x200>; 133 #size-cells = <0>;
172 interrupts = <0 19 0x04>; 134 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
135 reg = <0x7000c500 0x100>;
136 interrupts = <0 92 0x04>;
173 }; 137 };
174 138
175 sdhci@78000600 { 139 i2c@7000c700 {
176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 140 #address-cells = <1>;
177 reg = <0x78000600 0x200>; 141 #size-cells = <0>;
178 interrupts = <0 31 0x04>; 142 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
143 reg = <0x7000c700 0x100>;
144 interrupts = <0 120 0x04>;
179 }; 145 };
180 146
181 pinmux: pinmux { 147 i2c@7000d000 {
182 compatible = "nvidia,tegra30-pinmux"; 148 #address-cells = <1>;
183 reg = <0x70000868 0xd0 /* Pad control registers */ 149 #size-cells = <0>;
184 0x70003000 0x3e0>; /* Mux registers */ 150 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
151 reg = <0x7000d000 0x100>;
152 interrupts = <0 53 0x04>;
153 };
154
155 pmc {
156 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
157 reg = <0x7000e400 0x400>;
158 };
159
160 mc {
161 compatible = "nvidia,tegra30-mc";
162 reg = <0x7000f000 0x010
163 0x7000f03c 0x1b4
164 0x7000f200 0x028
165 0x7000f284 0x17c>;
166 interrupts = <0 77 0x04>;
167 };
168
169 smmu {
170 compatible = "nvidia,tegra30-smmu";
171 reg = <0x7000f010 0x02c
172 0x7000f1f0 0x010
173 0x7000f228 0x05c>;
174 nvidia,#asids = <4>; /* # of ASIDs */
175 dma-window = <0 0x40000000>; /* IOVA start & length */
176 nvidia,ahb = <&ahb>;
185 }; 177 };
186 178
187 ahub { 179 ahub {
@@ -226,27 +218,35 @@
226 }; 218 };
227 }; 219 };
228 220
229 ahb: ahb { 221 sdhci@78000000 {
230 compatible = "nvidia,tegra30-ahb"; 222 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
231 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ 223 reg = <0x78000000 0x200>;
224 interrupts = <0 14 0x04>;
232 }; 225 };
233 226
234 mc { 227 sdhci@78000200 {
235 compatible = "nvidia,tegra30-mc"; 228 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
236 reg = <0x7000f000 0x010 229 reg = <0x78000200 0x200>;
237 0x7000f03c 0x1b4 230 interrupts = <0 15 0x04>;
238 0x7000f200 0x028
239 0x7000f284 0x17c>;
240 interrupts = <0 77 0x04>;
241 }; 231 };
242 232
243 smmu { 233 sdhci@78000400 {
244 compatible = "nvidia,tegra30-smmu"; 234 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
245 reg = <0x7000f010 0x02c 235 reg = <0x78000400 0x200>;
246 0x7000f1f0 0x010 236 interrupts = <0 19 0x04>;
247 0x7000f228 0x05c>; 237 };
248 nvidia,#asids = <4>; /* # of ASIDs */ 238
249 dma-window = <0 0x40000000>; /* IOVA start & length */ 239 sdhci@78000600 {
250 nvidia,ahb = <&ahb>; 240 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
241 reg = <0x78000600 0x200>;
242 interrupts = <0 31 0x04>;
243 };
244
245 pmu {
246 compatible = "arm,cortex-a9-pmu";
247 interrupts = <0 144 0x04
248 0 145 0x04
249 0 146 0x04
250 0 147 0x04>;
251 }; 251 };
252}; 252};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 10:32:30 -0500