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authorArnd Bergmann <arnd@arndb.de>2015-03-04 16:55:23 -0500
committerArnd Bergmann <arnd@arndb.de>2015-03-04 16:56:06 -0500
commit605e0f904bb6b9ba13f8d7918f3c016ac00b86bc (patch)
tree1708074148678df0abd2b86038489de08bfbf336 /arch/arm/boot
parent756c08b068712dec875614f27ccbc38fdeda4fe7 (diff)
parentc6535e1e0361157ea073b57b626d0611b7c4c7a0 (diff)
Merge tag 'renesas-sh7372-soc-removal-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Pull "Renesas ARM Based SoC sh7372 SoC Removal Updates for v4.1" from Simon Horman: * Remove the sh7372 SoC and its mackerel board * tag 'renesas-sh7372-soc-removal-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: Documentation: Remove ZBOOT MMC/SDHI utility and docs ARM: shmobile: sh7372 dtsi: Remove Legacy DTSI file ARM: shmobile: sh7372: Remove DT binding documentation ARM: shmobile: sh7372: Remove Legacy C SoC code ARM: shmobile: sh7372: Remove ZBOOT MMC/SDHI support ARM: shmobile: mackerel: Remove from MAINTAINERS ARM: shmobile: mackerel: Remove defconfig ARM: shmobile: mackerel: Remove mach-type entry ARM: shmobile: mackerel: Remove DT binding documentation ARM: shmobile: mackerel dts: Remove Legacy DTS file ARM: shmobile: mackerel: Remove Legacy C board code ARM: shmobile: mackerel: Remove ZBOOT code [arnd: The sh7372 platform is rather dated and is believed to have no active users on modern kernels. It stands in the way of converting all of mach-shmobile to be multiplatform capable, as adding pinctrl and common-clock support for it would be more work than it's worth. As always, should any legitimate upstream users show up in the future, we will revert this removal]
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/Makefile15
-rw-r--r--arch/arm/boot/compressed/head-shmobile.S30
-rw-r--r--arch/arm/boot/compressed/mmcif-sh7372.c88
-rw-r--r--arch/arm/boot/compressed/sdhi-sh7372.c95
-rw-r--r--arch/arm/boot/compressed/sdhi-shmobile.c449
-rw-r--r--arch/arm/boot/compressed/sdhi-shmobile.h11
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/sh7372-mackerel.dts26
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi35
9 files changed, 0 insertions, 750 deletions
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3ea230aa94b7..6e1fb2b2ecc7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -6,21 +6,6 @@
6 6
7OBJS = 7OBJS =
8 8
9# Ensure that MMCIF loader code appears early in the image
10# to minimise that number of bocks that have to be read in
11# order to load it.
12ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y)
13OBJS += mmcif-sh7372.o
14endif
15
16# Ensure that SDHI loader code appears early in the image
17# to minimise that number of bocks that have to be read in
18# order to load it.
19ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y)
20OBJS += sdhi-shmobile.o
21OBJS += sdhi-sh7372.o
22endif
23
24AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) 9AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
25HEAD = head.o 10HEAD = head.o
26OBJS += misc.o decompress.o 11OBJS += misc.o decompress.o
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index e7f80928949c..22a75259faa3 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -25,36 +25,6 @@
25 /* load board-specific initialization code */ 25 /* load board-specific initialization code */
26#include <mach/zboot.h> 26#include <mach/zboot.h>
27 27
28#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
29 /* Load image from MMC/SD */
30 adr sp, __tmp_stack + 256
31 ldr r0, __image_start
32 ldr r1, __image_end
33 subs r1, r1, r0
34 ldr r0, __load_base
35 bl mmc_loader
36
37 /* Jump to loaded code */
38 ldr r0, __loaded
39 ldr r1, __image_start
40 sub r0, r0, r1
41 ldr r1, __load_base
42 add pc, r0, r1
43
44__image_start:
45 .long _start
46__image_end:
47 .long _got_end
48__load_base:
49 .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
50__loaded:
51 .long __continue
52 .align
53__tmp_stack:
54 .space 256
55__continue:
56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
57
58 adr r0, dtb_info 28 adr r0, dtb_info
59 ldmia r0, {r1, r3, r4, r5, r7} 29 ldmia r0, {r1, r3, r4, r5, r7}
60 30
diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c
deleted file mode 100644
index 672ae95db5c3..000000000000
--- a/arch/arm/boot/compressed/mmcif-sh7372.c
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * sh7372 MMCIF loader
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Simon Horman
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/mmc/sh_mmcif.h>
13#include <linux/mmc/boot.h>
14#include <mach/mmc.h>
15
16#define MMCIF_BASE (void __iomem *)0xe6bd0000
17
18#define PORT84CR (void __iomem *)0xe6050054
19#define PORT85CR (void __iomem *)0xe6050055
20#define PORT86CR (void __iomem *)0xe6050056
21#define PORT87CR (void __iomem *)0xe6050057
22#define PORT88CR (void __iomem *)0xe6050058
23#define PORT89CR (void __iomem *)0xe6050059
24#define PORT90CR (void __iomem *)0xe605005a
25#define PORT91CR (void __iomem *)0xe605005b
26#define PORT92CR (void __iomem *)0xe605005c
27#define PORT99CR (void __iomem *)0xe6050063
28
29#define SMSTPCR3 (void __iomem *)0xe615013c
30
31/* SH7372 specific MMCIF loader
32 *
33 * loads the zImage from an MMC card starting from block 1.
34 *
35 * The image must be start with a vrl4 header and
36 * the zImage must start at offset 512 of the image. That is,
37 * at block 2 (=byte 1024) on the media
38 *
39 * Use the following line to write the vrl4 formated zImage
40 * to an MMC card
41 * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
42 */
43asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
44{
45 mmc_init_progress();
46 mmc_update_progress(MMC_PROGRESS_ENTER);
47
48 /* Initialise MMC
49 * registers: PORT84CR-PORT92CR
50 * (MMCD0_0-MMCD0_7,MMCCMD0 Control)
51 * value: 0x04 - select function 4
52 */
53 __raw_writeb(0x04, PORT84CR);
54 __raw_writeb(0x04, PORT85CR);
55 __raw_writeb(0x04, PORT86CR);
56 __raw_writeb(0x04, PORT87CR);
57 __raw_writeb(0x04, PORT88CR);
58 __raw_writeb(0x04, PORT89CR);
59 __raw_writeb(0x04, PORT90CR);
60 __raw_writeb(0x04, PORT91CR);
61 __raw_writeb(0x04, PORT92CR);
62
63 /* Initialise MMC
64 * registers: PORT99CR (MMCCLK0 Control)
65 * value: 0x10 | 0x04 - enable output | select function 4
66 */
67 __raw_writeb(0x14, PORT99CR);
68
69 /* Enable clock to MMC hardware block */
70 __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);
71
72 mmc_update_progress(MMC_PROGRESS_INIT);
73
74 /* setup MMCIF hardware */
75 sh_mmcif_boot_init(MMCIF_BASE);
76
77 mmc_update_progress(MMC_PROGRESS_LOAD);
78
79 /* load kernel via MMCIF interface */
80 sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */
81 (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);
82
83
84 /* Disable clock to MMC hardware block */
85 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
86
87 mmc_update_progress(MMC_PROGRESS_DONE);
88}
diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c
deleted file mode 100644
index d279294f2381..000000000000
--- a/arch/arm/boot/compressed/sdhi-sh7372.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * SuperH Mobile SDHI
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 * Parts inspired by u-boot
13 */
14
15#include <linux/io.h>
16#include <mach/mmc.h>
17#include <linux/mmc/boot.h>
18#include <linux/mmc/tmio.h>
19
20#include "sdhi-shmobile.h"
21
22#define PORT179CR 0xe60520b3
23#define PORT180CR 0xe60520b4
24#define PORT181CR 0xe60520b5
25#define PORT182CR 0xe60520b6
26#define PORT183CR 0xe60520b7
27#define PORT184CR 0xe60520b8
28
29#define SMSTPCR3 0xe615013c
30
31#define CR_INPUT_ENABLE 0x10
32#define CR_FUNCTION1 0x01
33
34#define SDHI1_BASE (void __iomem *)0xe6860000
35#define SDHI_BASE SDHI1_BASE
36
37/* SuperH Mobile SDHI loader
38 *
39 * loads the zImage from an SD card starting from block 0
40 * on physical partition 1
41 *
42 * The image must be start with a vrl4 header and
43 * the zImage must start at offset 512 of the image. That is,
44 * at block 1 (=byte 512) of physical partition 1
45 *
46 * Use the following line to write the vrl4 formated zImage
47 * to an SD card
48 * # dd if=vrl4.out of=/dev/sdx bs=512
49 */
50asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
51{
52 int high_capacity;
53
54 mmc_init_progress();
55
56 mmc_update_progress(MMC_PROGRESS_ENTER);
57 /* Initialise SDHI1 */
58 /* PORT184CR: GPIO_FN_SDHICMD1 Control */
59 __raw_writeb(CR_FUNCTION1, PORT184CR);
60 /* PORT179CR: GPIO_FN_SDHICLK1 Control */
61 __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR);
62 /* PORT181CR: GPIO_FN_SDHID1_3 Control */
63 __raw_writeb(CR_FUNCTION1, PORT183CR);
64 /* PORT182CR: GPIO_FN_SDHID1_2 Control */
65 __raw_writeb(CR_FUNCTION1, PORT182CR);
66 /* PORT183CR: GPIO_FN_SDHID1_1 Control */
67 __raw_writeb(CR_FUNCTION1, PORT181CR);
68 /* PORT180CR: GPIO_FN_SDHID1_0 Control */
69 __raw_writeb(CR_FUNCTION1, PORT180CR);
70
71 /* Enable clock to SDHI1 hardware block */
72 __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3);
73
74 /* setup SDHI hardware */
75 mmc_update_progress(MMC_PROGRESS_INIT);
76 high_capacity = sdhi_boot_init(SDHI_BASE);
77 if (high_capacity < 0)
78 goto err;
79
80 mmc_update_progress(MMC_PROGRESS_LOAD);
81 /* load kernel */
82 if (sdhi_boot_do_read(SDHI_BASE, high_capacity,
83 0, /* Kernel is at block 1 */
84 (len + TMIO_BBS - 1) / TMIO_BBS, buf))
85 goto err;
86
87 /* Disable clock to SDHI1 hardware block */
88 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
89
90 mmc_update_progress(MMC_PROGRESS_DONE);
91
92 return;
93err:
94 for(;;);
95}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
deleted file mode 100644
index bd3d46980955..000000000000
--- a/arch/arm/boot/compressed/sdhi-shmobile.c
+++ /dev/null
@@ -1,449 +0,0 @@
1/*
2 * SuperH Mobile SDHI
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 * Parts inspired by u-boot
13 */
14
15#include <linux/io.h>
16#include <linux/mmc/host.h>
17#include <linux/mmc/core.h>
18#include <linux/mmc/mmc.h>
19#include <linux/mmc/sd.h>
20#include <linux/mmc/tmio.h>
21#include <mach/sdhi.h>
22
23#define OCR_FASTBOOT (1<<29)
24#define OCR_HCS (1<<30)
25#define OCR_BUSY (1<<31)
26
27#define RESP_CMD12 0x00000030
28
29static inline u16 sd_ctrl_read16(void __iomem *base, int addr)
30{
31 return __raw_readw(base + addr);
32}
33
34static inline u32 sd_ctrl_read32(void __iomem *base, int addr)
35{
36 return __raw_readw(base + addr) |
37 __raw_readw(base + addr + 2) << 16;
38}
39
40static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val)
41{
42 __raw_writew(val, base + addr);
43}
44
45static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val)
46{
47 __raw_writew(val, base + addr);
48 __raw_writew(val >> 16, base + addr + 2);
49}
50
51#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \
52 TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \
53 TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \
54 TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \
55 TMIO_STAT_ILL_FUNC)
56
57static int sdhi_intr(void __iomem *base)
58{
59 unsigned long state = sd_ctrl_read32(base, CTL_STATUS);
60
61 if (state & ALL_ERROR) {
62 sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR);
63 sd_ctrl_write32(base, CTL_IRQ_MASK,
64 ALL_ERROR |
65 sd_ctrl_read32(base, CTL_IRQ_MASK));
66 return -EINVAL;
67 }
68 if (state & TMIO_STAT_CMDRESPEND) {
69 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
70 sd_ctrl_write32(base, CTL_IRQ_MASK,
71 TMIO_STAT_CMDRESPEND |
72 sd_ctrl_read32(base, CTL_IRQ_MASK));
73 return 0;
74 }
75 if (state & TMIO_STAT_RXRDY) {
76 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY);
77 sd_ctrl_write32(base, CTL_IRQ_MASK,
78 TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN |
79 sd_ctrl_read32(base, CTL_IRQ_MASK));
80 return 0;
81 }
82 if (state & TMIO_STAT_DATAEND) {
83 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND);
84 sd_ctrl_write32(base, CTL_IRQ_MASK,
85 TMIO_STAT_DATAEND |
86 sd_ctrl_read32(base, CTL_IRQ_MASK));
87 return 0;
88 }
89
90 return -EAGAIN;
91}
92
93static int sdhi_boot_wait_resp_end(void __iomem *base)
94{
95 int err = -EAGAIN, timeout = 10000000;
96
97 while (timeout--) {
98 err = sdhi_intr(base);
99 if (err != -EAGAIN)
100 break;
101 udelay(1);
102 }
103
104 return err;
105}
106
107/* SDHI_CLK_CTRL */
108#define CLK_MMC_ENABLE (1 << 8)
109#define CLK_MMC_INIT (1 << 6) /* clk / 256 */
110
111static void sdhi_boot_mmc_clk_stop(void __iomem *base)
112{
113 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000);
114 msleep(10);
115 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE &
116 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
117 msleep(10);
118}
119
120static void sdhi_boot_mmc_clk_start(void __iomem *base)
121{
122 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE |
123 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
124 msleep(10);
125 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE);
126 msleep(10);
127}
128
129static void sdhi_boot_reset(void __iomem *base)
130{
131 sd_ctrl_write16(base, CTL_RESET_SD, 0x0000);
132 msleep(10);
133 sd_ctrl_write16(base, CTL_RESET_SD, 0x0001);
134 msleep(10);
135}
136
137/* Set MMC clock / power.
138 * Note: This controller uses a simple divider scheme therefore it cannot
139 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
140 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
141 * slowest setting.
142 */
143static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios)
144{
145 if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY)
146 return -EBUSY;
147
148 if (ios->clock)
149 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL,
150 ios->clock | CLK_MMC_ENABLE);
151
152 /* Power sequence - OFF -> ON -> UP */
153 switch (ios->power_mode) {
154 case MMC_POWER_OFF: /* power down SD bus */
155 sdhi_boot_mmc_clk_stop(base);
156 break;
157 case MMC_POWER_ON: /* power up SD bus */
158 break;
159 case MMC_POWER_UP: /* start bus clock */
160 sdhi_boot_mmc_clk_start(base);
161 break;
162 }
163
164 switch (ios->bus_width) {
165 case MMC_BUS_WIDTH_1:
166 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0);
167 break;
168 case MMC_BUS_WIDTH_4:
169 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0);
170 break;
171 }
172
173 /* Let things settle. delay taken from winCE driver */
174 udelay(140);
175
176 return 0;
177}
178
179/* These are the bitmasks the tmio chip requires to implement the MMC response
180 * types. Note that R1 and R6 are the same in this scheme. */
181#define RESP_NONE 0x0300
182#define RESP_R1 0x0400
183#define RESP_R1B 0x0500
184#define RESP_R2 0x0600
185#define RESP_R3 0x0700
186#define DATA_PRESENT 0x0800
187#define TRANSFER_READ 0x1000
188
189static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd)
190{
191 int err, c = cmd->opcode;
192
193 switch (mmc_resp_type(cmd)) {
194 case MMC_RSP_NONE: c |= RESP_NONE; break;
195 case MMC_RSP_R1: c |= RESP_R1; break;
196 case MMC_RSP_R1B: c |= RESP_R1B; break;
197 case MMC_RSP_R2: c |= RESP_R2; break;
198 case MMC_RSP_R3: c |= RESP_R3; break;
199 default:
200 return -EINVAL;
201 }
202
203 /* No interrupts so this may not be cleared */
204 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
205
206 sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND |
207 sd_ctrl_read32(base, CTL_IRQ_MASK));
208 sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg);
209 sd_ctrl_write16(base, CTL_SD_CMD, c);
210
211
212 sd_ctrl_write32(base, CTL_IRQ_MASK,
213 ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) &
214 sd_ctrl_read32(base, CTL_IRQ_MASK));
215
216 err = sdhi_boot_wait_resp_end(base);
217 if (err)
218 return err;
219
220 cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE);
221
222 return 0;
223}
224
225static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity,
226 unsigned long block, unsigned short *buf)
227{
228 int err, i;
229
230 /* CMD17 - Read */
231 {
232 struct mmc_command cmd;
233
234 cmd.opcode = MMC_READ_SINGLE_BLOCK | \
235 TRANSFER_READ | DATA_PRESENT;
236 if (high_capacity)
237 cmd.arg = block;
238 else
239 cmd.arg = block * TMIO_BBS;
240 cmd.flags = MMC_RSP_R1;
241 err = sdhi_boot_request(base, &cmd);
242 if (err)
243 return err;
244 }
245
246 sd_ctrl_write32(base, CTL_IRQ_MASK,
247 ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY |
248 TMIO_STAT_TXUNDERRUN) &
249 sd_ctrl_read32(base, CTL_IRQ_MASK));
250 err = sdhi_boot_wait_resp_end(base);
251 if (err)
252 return err;
253
254 sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS);
255 for (i = 0; i < TMIO_BBS / sizeof(*buf); i++)
256 *buf++ = sd_ctrl_read16(base, RESP_CMD12);
257
258 err = sdhi_boot_wait_resp_end(base);
259 if (err)
260 return err;
261
262 return 0;
263}
264
265int sdhi_boot_do_read(void __iomem *base, int high_capacity,
266 unsigned long offset, unsigned short count,
267 unsigned short *buf)
268{
269 unsigned long i;
270 int err = 0;
271
272 for (i = 0; i < count; i++) {
273 err = sdhi_boot_do_read_single(base, high_capacity, offset + i,
274 buf + (i * TMIO_BBS /
275 sizeof(*buf)));
276 if (err)
277 return err;
278 }
279
280 return 0;
281}
282
283#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34)
284
285int sdhi_boot_init(void __iomem *base)
286{
287 bool sd_v2 = false, sd_v1_0 = false;
288 unsigned short cid;
289 int err, high_capacity = 0;
290
291 sdhi_boot_mmc_clk_stop(base);
292 sdhi_boot_reset(base);
293
294 /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */
295 {
296 struct mmc_ios ios;
297 ios.power_mode = MMC_POWER_ON;
298 ios.bus_width = MMC_BUS_WIDTH_1;
299 ios.clock = CLK_MMC_INIT;
300 err = sdhi_boot_mmc_set_ios(base, &ios);
301 if (err)
302 return err;
303 }
304
305 /* CMD0 */
306 {
307 struct mmc_command cmd;
308 msleep(1);
309 cmd.opcode = MMC_GO_IDLE_STATE;
310 cmd.arg = 0;
311 cmd.flags = MMC_RSP_NONE;
312 err = sdhi_boot_request(base, &cmd);
313 if (err)
314 return err;
315 msleep(2);
316 }
317
318 /* CMD8 - Test for SD version 2 */
319 {
320 struct mmc_command cmd;
321 cmd.opcode = SD_SEND_IF_COND;
322 cmd.arg = (VOLTAGES != 0) << 8 | 0xaa;
323 cmd.flags = MMC_RSP_R1;
324 err = sdhi_boot_request(base, &cmd); /* Ignore error */
325 if ((cmd.resp[0] & 0xff) == 0xaa)
326 sd_v2 = true;
327 }
328
329 /* CMD55 - Get OCR (SD) */
330 {
331 int timeout = 1000;
332 struct mmc_command cmd;
333
334 cmd.arg = 0;
335
336 do {
337 cmd.opcode = MMC_APP_CMD;
338 cmd.flags = MMC_RSP_R1;
339 cmd.arg = 0;
340 err = sdhi_boot_request(base, &cmd);
341 if (err)
342 break;
343
344 cmd.opcode = SD_APP_OP_COND;
345 cmd.flags = MMC_RSP_R3;
346 cmd.arg = (VOLTAGES & 0xff8000);
347 if (sd_v2)
348 cmd.arg |= OCR_HCS;
349 cmd.arg |= OCR_FASTBOOT;
350 err = sdhi_boot_request(base, &cmd);
351 if (err)
352 break;
353
354 msleep(1);
355 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
356
357 if (!err && timeout) {
358 if (!sd_v2)
359 sd_v1_0 = true;
360 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
361 }
362 }
363
364 /* CMD1 - Get OCR (MMC) */
365 if (!sd_v2 && !sd_v1_0) {
366 int timeout = 1000;
367 struct mmc_command cmd;
368
369 do {
370 cmd.opcode = MMC_SEND_OP_COND;
371 cmd.arg = VOLTAGES | OCR_HCS;
372 cmd.flags = MMC_RSP_R3;
373 err = sdhi_boot_request(base, &cmd);
374 if (err)
375 return err;
376
377 msleep(1);
378 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
379
380 if (!timeout)
381 return -EAGAIN;
382
383 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
384 }
385
386 /* CMD2 - Get CID */
387 {
388 struct mmc_command cmd;
389 cmd.opcode = MMC_ALL_SEND_CID;
390 cmd.arg = 0;
391 cmd.flags = MMC_RSP_R2;
392 err = sdhi_boot_request(base, &cmd);
393 if (err)
394 return err;
395 }
396
397 /* CMD3
398 * MMC: Set the relative address
399 * SD: Get the relative address
400 * Also puts the card into the standby state
401 */
402 {
403 struct mmc_command cmd;
404 cmd.opcode = MMC_SET_RELATIVE_ADDR;
405 cmd.arg = 0;
406 cmd.flags = MMC_RSP_R1;
407 err = sdhi_boot_request(base, &cmd);
408 if (err)
409 return err;
410 cid = cmd.resp[0] >> 16;
411 }
412
413 /* CMD9 - Get CSD */
414 {
415 struct mmc_command cmd;
416 cmd.opcode = MMC_SEND_CSD;
417 cmd.arg = cid << 16;
418 cmd.flags = MMC_RSP_R2;
419 err = sdhi_boot_request(base, &cmd);
420 if (err)
421 return err;
422 }
423
424 /* CMD7 - Select the card */
425 {
426 struct mmc_command cmd;
427 cmd.opcode = MMC_SELECT_CARD;
428 //cmd.arg = rca << 16;
429 cmd.arg = cid << 16;
430 //cmd.flags = MMC_RSP_R1B;
431 cmd.flags = MMC_RSP_R1;
432 err = sdhi_boot_request(base, &cmd);
433 if (err)
434 return err;
435 }
436
437 /* CMD16 - Set the block size */
438 {
439 struct mmc_command cmd;
440 cmd.opcode = MMC_SET_BLOCKLEN;
441 cmd.arg = TMIO_BBS;
442 cmd.flags = MMC_RSP_R1;
443 err = sdhi_boot_request(base, &cmd);
444 if (err)
445 return err;
446 }
447
448 return high_capacity;
449}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.h b/arch/arm/boot/compressed/sdhi-shmobile.h
deleted file mode 100644
index 92eaa09f985e..000000000000
--- a/arch/arm/boot/compressed/sdhi-shmobile.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef SDHI_MOBILE_H
2#define SDHI_MOBILE_H
3
4#include <linux/compiler.h>
5
6int sdhi_boot_do_read(void __iomem *base, int high_capacity,
7 unsigned long offset, unsigned short count,
8 unsigned short *buf);
9int sdhi_boot_init(void __iomem *base);
10
11#endif
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b8dcec..0d467b877ec7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -470,7 +470,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
470 r8a7778-bockw.dtb \ 470 r8a7778-bockw.dtb \
471 r8a7778-bockw-reference.dtb \ 471 r8a7778-bockw-reference.dtb \
472 r8a7779-marzen.dtb \ 472 r8a7779-marzen.dtb \
473 sh7372-mackerel.dtb \
474 sh73a0-kzm9g.dtb \ 473 sh73a0-kzm9g.dtb \
475 sh73a0-kzm9g-reference.dtb 474 sh73a0-kzm9g-reference.dtb
476dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ 475dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
deleted file mode 100644
index a759a276c9a9..000000000000
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Device Tree Source for the mackerel board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "sh7372.dtsi"
13
14/ {
15 model = "Mackerel (AP4 EVM 2nd)";
16 compatible = "renesas,mackerel";
17
18 chosen {
19 bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x40000000 0x10000000>;
25 };
26};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
deleted file mode 100644
index f863a10cb1b2..000000000000
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Device Tree Source for the sh7372 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7372";
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 device_type = "cpu";
23 reg = <0x0>;
24 clock-frequency = <800000000>;
25 };
26 };
27
28 pfc: pfc@e6050000 {
29 compatible = "renesas,pfc-sh7372";
30 reg = <0xe6050000 0x8000>,
31 <0xe605801c 0x1c>;
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35};