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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-02 00:08:03 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-02 00:08:03 -0400
commit994c0e992522c123298b4a91b72f5e67ba2d1123 (patch)
tree411952f844b8e1d5ef2854e44df793529078d3eb /arch/arm/boot
parent367069f16e32e188d4687fe2c3e30f2ca583836f (diff)
parentabc3f126ac736280c68db6472eb0040ddf6e1b1f (diff)
Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc
* 'next/soc' of git://git.linaro.org/people/arnd/arm-soc: (21 commits) MAINTAINERS: add ARM/FREESCALE IMX6 entry arm/imx: merge i.MX3 and i.MX6 arm/imx6q: add suspend/resume support arm/imx6q: add device tree machine support arm/imx6q: add smp and cpu hotplug support arm/imx6q: add core drivers clock, gpc, mmdc and src arm/imx: add gic_handle_irq function arm/imx6q: add core definitions and low-level debug uart arm/imx6q: add device tree source ARM: highbank: add suspend support ARM: highbank: Add cpu hotplug support ARM: highbank: add SMP support MAINTAINERS: add Calxeda Highbank ARM platform ARM: add Highbank core platform support ARM: highbank: add devicetree source ARM: l2x0: add empty l2x0_of_init picoxcell: add a definition of VMALLOC_END picoxcell: remove custom ioremap implementation picoxcell: add the DTS for the PC7302 board picoxcell: add the DTS for pc3x2 and pc3x3 devices ... Fix up trivial conflicts in arch/arm/Kconfig, and some more header file conflicts in arch/arm/mach-omap2/board-generic.c (as per an ealier merge by Arnd).
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/highbank.dts198
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts62
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi575
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x2.dtsi249
-rw-r--r--arch/arm/boot/dts/picoxcell-pc3x3.dtsi365
-rw-r--r--arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts86
-rw-r--r--arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts92
7 files changed, 1627 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
new file mode 100644
index 000000000000..aeb1a7578fad
--- /dev/null
+++ b/arch/arm/boot/dts/highbank.dts
@@ -0,0 +1,198 @@
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23 model = "Calxeda Highbank";
24 compatible = "calxeda,highbank";
25 #address-cells = <1>;
26 #size-cells = <1>;
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 compatible = "arm,cortex-a9";
34 reg = <0>;
35 next-level-cache = <&L2>;
36 };
37
38 cpu@1 {
39 compatible = "arm,cortex-a9";
40 reg = <1>;
41 next-level-cache = <&L2>;
42 };
43
44 cpu@2 {
45 compatible = "arm,cortex-a9";
46 reg = <2>;
47 next-level-cache = <&L2>;
48 };
49
50 cpu@3 {
51 compatible = "arm,cortex-a9";
52 reg = <3>;
53 next-level-cache = <&L2>;
54 };
55 };
56
57 memory {
58 name = "memory";
59 device_type = "memory";
60 reg = <0x00000000 0xff900000>;
61 };
62
63 chosen {
64 bootargs = "console=ttyAMA0";
65 };
66
67 soc {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&intc>;
72 ranges;
73
74 timer@fff10600 {
75 compatible = "arm,smp-twd";
76 reg = <0xfff10600 0x20>;
77 interrupts = <1 13 0xf04>;
78 };
79
80 watchdog@fff10620 {
81 compatible = "arm,cortex-a9-wdt";
82 reg = <0xfff10620 0x20>;
83 interrupts = <1 14 0xf04>;
84 };
85
86 intc: interrupt-controller@fff11000 {
87 compatible = "arm,cortex-a9-gic";
88 #interrupt-cells = <3>;
89 #size-cells = <0>;
90 #address-cells = <1>;
91 interrupt-controller;
92 interrupt-parent;
93 reg = <0xfff11000 0x1000>,
94 <0xfff10100 0x100>;
95 };
96
97 L2: l2-cache {
98 compatible = "arm,pl310-cache";
99 reg = <0xfff12000 0x1000>;
100 interrupts = <0 70 4>;
101 cache-unified;
102 cache-level = <2>;
103 };
104
105 pmu {
106 compatible = "arm,cortex-a9-pmu";
107 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
108 };
109
110 sata@ffe08000 {
111 compatible = "calxeda,hb-ahci";
112 reg = <0xffe08000 0x10000>;
113 interrupts = <0 83 4>;
114 };
115
116 sdhci@ffe0e000 {
117 compatible = "calxeda,hb-sdhci";
118 reg = <0xffe0e000 0x1000>;
119 interrupts = <0 90 4>;
120 };
121
122 ipc@fff20000 {
123 compatible = "arm,pl320", "arm,primecell";
124 reg = <0xfff20000 0x1000>;
125 interrupts = <0 7 4>;
126 };
127
128 gpioe: gpio@fff30000 {
129 #gpio-cells = <2>;
130 compatible = "arm,pl061", "arm,primecell";
131 gpio-controller;
132 reg = <0xfff30000 0x1000>;
133 interrupts = <0 14 4>;
134 };
135
136 gpiof: gpio@fff31000 {
137 #gpio-cells = <2>;
138 compatible = "arm,pl061", "arm,primecell";
139 gpio-controller;
140 reg = <0xfff31000 0x1000>;
141 interrupts = <0 15 4>;
142 };
143
144 gpiog: gpio@fff32000 {
145 #gpio-cells = <2>;
146 compatible = "arm,pl061", "arm,primecell";
147 gpio-controller;
148 reg = <0xfff32000 0x1000>;
149 interrupts = <0 16 4>;
150 };
151
152 gpioh: gpio@fff33000 {
153 #gpio-cells = <2>;
154 compatible = "arm,pl061", "arm,primecell";
155 gpio-controller;
156 reg = <0xfff33000 0x1000>;
157 interrupts = <0 17 4>;
158 };
159
160 timer {
161 compatible = "arm,sp804", "arm,primecell";
162 reg = <0xfff34000 0x1000>;
163 interrupts = <0 18 4>;
164 };
165
166 rtc@fff35000 {
167 compatible = "arm,pl031", "arm,primecell";
168 reg = <0xfff35000 0x1000>;
169 interrupts = <0 19 4>;
170 };
171
172 serial@fff36000 {
173 compatible = "arm,pl011", "arm,primecell";
174 reg = <0xfff36000 0x1000>;
175 interrupts = <0 20 4>;
176 };
177
178 smic@fff3a000 {
179 compatible = "ipmi-smic";
180 device_type = "ipmi";
181 reg = <0xfff3a000 0x1000>;
182 interrupts = <0 24 4>;
183 reg-size = <4>;
184 reg-spacing = <4>;
185 };
186
187 sregs@fff3c000 {
188 compatible = "calxeda,hb-sregs";
189 reg = <0xfff3c000 0x1000>;
190 };
191
192 dma@fff3d000 {
193 compatible = "arm,pl330", "arm,primecell";
194 reg = <0xfff3d000 0x1000>;
195 interrupts = <0 92 4>;
196 };
197 };
198};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
new file mode 100644
index 000000000000..072974e443f2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Automotive Board";
18 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
22 };
23
24 memory {
25 reg = <0x10000000 0x80000000>;
26 };
27
28 soc {
29 aips-bus@02100000 { /* AIPS2 */
30 enet@02188000 {
31 phy-mode = "rgmii";
32 local-mac-address = [00 04 9F 01 1B 61];
33 status = "okay";
34 };
35
36 usdhc@02198000 { /* uSDHC3 */
37 cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
38 wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
39 status = "okay";
40 };
41
42 usdhc@0219c000 { /* uSDHC4 */
43 fsl,card-wired;
44 status = "okay";
45 };
46
47 uart3: uart@021f0000 { /* UART4 */
48 status = "okay";
49 };
50 };
51 };
52
53 leds {
54 compatible = "gpio-leds";
55
56 debug-led {
57 label = "Heartbeat";
58 gpios = <&gpio2 25 0>; /* GPIO3_25 */
59 linux,default-trigger = "heartbeat";
60 };
61 };
62};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
new file mode 100644
index 000000000000..7dda599558cc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -0,0 +1,575 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 serial3 = &uart3;
21 serial4 = &uart4;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 compatible = "arm,cortex-a9";
30 reg = <0>;
31 next-level-cache = <&L2>;
32 };
33
34 cpu@1 {
35 compatible = "arm,cortex-a9";
36 reg = <1>;
37 next-level-cache = <&L2>;
38 };
39
40 cpu@2 {
41 compatible = "arm,cortex-a9";
42 reg = <2>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@3 {
47 compatible = "arm,cortex-a9";
48 reg = <3>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 intc: interrupt-controller@00a01000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 interrupt-controller;
59 reg = <0x00a01000 0x1000>,
60 <0x00a00100 0x100>;
61 };
62
63 clocks {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ckil {
68 compatible = "fsl,imx-ckil", "fixed-clock";
69 clock-frequency = <32768>;
70 };
71
72 ckih1 {
73 compatible = "fsl,imx-ckih1", "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 osc {
78 compatible = "fsl,imx-osc", "fixed-clock";
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&intc>;
88 ranges;
89
90 timer@00a00600 {
91 compatible = "arm,smp-twd";
92 reg = <0x00a00600 0x100>;
93 interrupts = <1 13 0xf4>;
94 };
95
96 L2: l2-cache@00a02000 {
97 compatible = "arm,pl310-cache";
98 reg = <0x00a02000 0x1000>;
99 interrupts = <0 92 0x04>;
100 cache-unified;
101 cache-level = <2>;
102 };
103
104 aips-bus@02000000 { /* AIPS1 */
105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x02000000 0x100000>;
109 ranges;
110
111 spba-bus@02000000 {
112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x02000000 0x40000>;
116 ranges;
117
118 spdif@02004000 {
119 reg = <0x02004000 0x4000>;
120 interrupts = <0 52 0x04>;
121 };
122
123 ecspi@02008000 { /* eCSPI1 */
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
127 reg = <0x02008000 0x4000>;
128 interrupts = <0 31 0x04>;
129 status = "disabled";
130 };
131
132 ecspi@0200c000 { /* eCSPI2 */
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
136 reg = <0x0200c000 0x4000>;
137 interrupts = <0 32 0x04>;
138 status = "disabled";
139 };
140
141 ecspi@02010000 { /* eCSPI3 */
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02010000 0x4000>;
146 interrupts = <0 33 0x04>;
147 status = "disabled";
148 };
149
150 ecspi@02014000 { /* eCSPI4 */
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
154 reg = <0x02014000 0x4000>;
155 interrupts = <0 34 0x04>;
156 status = "disabled";
157 };
158
159 ecspi@02018000 { /* eCSPI5 */
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
163 reg = <0x02018000 0x4000>;
164 interrupts = <0 35 0x04>;
165 status = "disabled";
166 };
167
168 uart0: uart@02020000 { /* UART1 */
169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>;
172 status = "disabled";
173 };
174
175 esai@02024000 {
176 reg = <0x02024000 0x4000>;
177 interrupts = <0 51 0x04>;
178 };
179
180 ssi@02028000 { /* SSI1 */
181 reg = <0x02028000 0x4000>;
182 interrupts = <0 46 0x04>;
183 };
184
185 ssi@0202c000 { /* SSI2 */
186 reg = <0x0202c000 0x4000>;
187 interrupts = <0 47 0x04>;
188 };
189
190 ssi@02030000 { /* SSI3 */
191 reg = <0x02030000 0x4000>;
192 interrupts = <0 48 0x04>;
193 };
194
195 asrc@02034000 {
196 reg = <0x02034000 0x4000>;
197 interrupts = <0 50 0x04>;
198 };
199
200 spba@0203c000 {
201 reg = <0x0203c000 0x4000>;
202 };
203 };
204
205 vpu@02040000 {
206 reg = <0x02040000 0x3c000>;
207 interrupts = <0 3 0x04 0 12 0x04>;
208 };
209
210 aipstz@0207c000 { /* AIPSTZ1 */
211 reg = <0x0207c000 0x4000>;
212 };
213
214 pwm@02080000 { /* PWM1 */
215 reg = <0x02080000 0x4000>;
216 interrupts = <0 83 0x04>;
217 };
218
219 pwm@02084000 { /* PWM2 */
220 reg = <0x02084000 0x4000>;
221 interrupts = <0 84 0x04>;
222 };
223
224 pwm@02088000 { /* PWM3 */
225 reg = <0x02088000 0x4000>;
226 interrupts = <0 85 0x04>;
227 };
228
229 pwm@0208c000 { /* PWM4 */
230 reg = <0x0208c000 0x4000>;
231 interrupts = <0 86 0x04>;
232 };
233
234 flexcan@02090000 { /* CAN1 */
235 reg = <0x02090000 0x4000>;
236 interrupts = <0 110 0x04>;
237 };
238
239 flexcan@02094000 { /* CAN2 */
240 reg = <0x02094000 0x4000>;
241 interrupts = <0 111 0x04>;
242 };
243
244 gpt@02098000 {
245 compatible = "fsl,imx6q-gpt";
246 reg = <0x02098000 0x4000>;
247 interrupts = <0 55 0x04>;
248 };
249
250 gpio0: gpio@0209c000 { /* GPIO1 */
251 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
252 reg = <0x0209c000 0x4000>;
253 interrupts = <0 66 0x04 0 67 0x04>;
254 gpio-controller;
255 #gpio-cells = <2>;
256 interrupt-controller;
257 #interrupt-cells = <1>;
258 };
259
260 gpio1: gpio@020a0000 { /* GPIO2 */
261 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
262 reg = <0x020a0000 0x4000>;
263 interrupts = <0 68 0x04 0 69 0x04>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
267 #interrupt-cells = <1>;
268 };
269
270 gpio2: gpio@020a4000 { /* GPIO3 */
271 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
272 reg = <0x020a4000 0x4000>;
273 interrupts = <0 70 0x04 0 71 0x04>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <1>;
278 };
279
280 gpio3: gpio@020a8000 { /* GPIO4 */
281 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
282 reg = <0x020a8000 0x4000>;
283 interrupts = <0 72 0x04 0 73 0x04>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <1>;
288 };
289
290 gpio4: gpio@020ac000 { /* GPIO5 */
291 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
292 reg = <0x020ac000 0x4000>;
293 interrupts = <0 74 0x04 0 75 0x04>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <1>;
298 };
299
300 gpio5: gpio@020b0000 { /* GPIO6 */
301 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
302 reg = <0x020b0000 0x4000>;
303 interrupts = <0 76 0x04 0 77 0x04>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <1>;
308 };
309
310 gpio6: gpio@020b4000 { /* GPIO7 */
311 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
312 reg = <0x020b4000 0x4000>;
313 interrupts = <0 78 0x04 0 79 0x04>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <1>;
318 };
319
320 kpp@020b8000 {
321 reg = <0x020b8000 0x4000>;
322 interrupts = <0 82 0x04>;
323 };
324
325 wdog@020bc000 { /* WDOG1 */
326 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
327 reg = <0x020bc000 0x4000>;
328 interrupts = <0 80 0x04>;
329 status = "disabled";
330 };
331
332 wdog@020c0000 { /* WDOG2 */
333 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
334 reg = <0x020c0000 0x4000>;
335 interrupts = <0 81 0x04>;
336 status = "disabled";
337 };
338
339 ccm@020c4000 {
340 compatible = "fsl,imx6q-ccm";
341 reg = <0x020c4000 0x4000>;
342 interrupts = <0 87 0x04 0 88 0x04>;
343 };
344
345 anatop@020c8000 {
346 compatible = "fsl,imx6q-anatop";
347 reg = <0x020c8000 0x1000>;
348 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
349 };
350
351 usbphy@020c9000 { /* USBPHY1 */
352 reg = <0x020c9000 0x1000>;
353 interrupts = <0 44 0x04>;
354 };
355
356 usbphy@020ca000 { /* USBPHY2 */
357 reg = <0x020ca000 0x1000>;
358 interrupts = <0 45 0x04>;
359 };
360
361 snvs@020cc000 {
362 reg = <0x020cc000 0x4000>;
363 interrupts = <0 19 0x04 0 20 0x04>;
364 };
365
366 epit@020d0000 { /* EPIT1 */
367 reg = <0x020d0000 0x4000>;
368 interrupts = <0 56 0x04>;
369 };
370
371 epit@020d4000 { /* EPIT2 */
372 reg = <0x020d4000 0x4000>;
373 interrupts = <0 57 0x04>;
374 };
375
376 src@020d8000 {
377 compatible = "fsl,imx6q-src";
378 reg = <0x020d8000 0x4000>;
379 interrupts = <0 91 0x04 0 96 0x04>;
380 };
381
382 gpc@020dc000 {
383 compatible = "fsl,imx6q-gpc";
384 reg = <0x020dc000 0x4000>;
385 interrupts = <0 89 0x04 0 90 0x04>;
386 };
387
388 iomuxc@020e0000 {
389 reg = <0x020e0000 0x4000>;
390 };
391
392 dcic@020e4000 { /* DCIC1 */
393 reg = <0x020e4000 0x4000>;
394 interrupts = <0 124 0x04>;
395 };
396
397 dcic@020e8000 { /* DCIC2 */
398 reg = <0x020e8000 0x4000>;
399 interrupts = <0 125 0x04>;
400 };
401
402 sdma@020ec000 {
403 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
404 reg = <0x020ec000 0x4000>;
405 interrupts = <0 2 0x04>;
406 };
407 };
408
409 aips-bus@02100000 { /* AIPS2 */
410 compatible = "fsl,aips-bus", "simple-bus";
411 #address-cells = <1>;
412 #size-cells = <1>;
413 reg = <0x02100000 0x100000>;
414 ranges;
415
416 caam@02100000 {
417 reg = <0x02100000 0x40000>;
418 interrupts = <0 105 0x04 0 106 0x04>;
419 };
420
421 aipstz@0217c000 { /* AIPSTZ2 */
422 reg = <0x0217c000 0x4000>;
423 };
424
425 enet@02188000 {
426 compatible = "fsl,imx6q-fec";
427 reg = <0x02188000 0x4000>;
428 interrupts = <0 118 0x04 0 119 0x04>;
429 status = "disabled";
430 };
431
432 mlb@0218c000 {
433 reg = <0x0218c000 0x4000>;
434 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
435 };
436
437 usdhc@02190000 { /* uSDHC1 */
438 compatible = "fsl,imx6q-usdhc";
439 reg = <0x02190000 0x4000>;
440 interrupts = <0 22 0x04>;
441 status = "disabled";
442 };
443
444 usdhc@02194000 { /* uSDHC2 */
445 compatible = "fsl,imx6q-usdhc";
446 reg = <0x02194000 0x4000>;
447 interrupts = <0 23 0x04>;
448 status = "disabled";
449 };
450
451 usdhc@02198000 { /* uSDHC3 */
452 compatible = "fsl,imx6q-usdhc";
453 reg = <0x02198000 0x4000>;
454 interrupts = <0 24 0x04>;
455 status = "disabled";
456 };
457
458 usdhc@0219c000 { /* uSDHC4 */
459 compatible = "fsl,imx6q-usdhc";
460 reg = <0x0219c000 0x4000>;
461 interrupts = <0 25 0x04>;
462 status = "disabled";
463 };
464
465 i2c@021a0000 { /* I2C1 */
466 #address-cells = <1>;
467 #size-cells = <0>;
468 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
469 reg = <0x021a0000 0x4000>;
470 interrupts = <0 36 0x04>;
471 status = "disabled";
472 };
473
474 i2c@021a4000 { /* I2C2 */
475 #address-cells = <1>;
476 #size-cells = <0>;
477 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
478 reg = <0x021a4000 0x4000>;
479 interrupts = <0 37 0x04>;
480 status = "disabled";
481 };
482
483 i2c@021a8000 { /* I2C3 */
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
487 reg = <0x021a8000 0x4000>;
488 interrupts = <0 38 0x04>;
489 status = "disabled";
490 };
491
492 romcp@021ac000 {
493 reg = <0x021ac000 0x4000>;
494 };
495
496 mmdc@021b0000 { /* MMDC0 */
497 compatible = "fsl,imx6q-mmdc";
498 reg = <0x021b0000 0x4000>;
499 };
500
501 mmdc@021b4000 { /* MMDC1 */
502 reg = <0x021b4000 0x4000>;
503 };
504
505 weim@021b8000 {
506 reg = <0x021b8000 0x4000>;
507 interrupts = <0 14 0x04>;
508 };
509
510 ocotp@021bc000 {
511 reg = <0x021bc000 0x4000>;
512 };
513
514 ocotp@021c0000 {
515 reg = <0x021c0000 0x4000>;
516 interrupts = <0 21 0x04>;
517 };
518
519 tzasc@021d0000 { /* TZASC1 */
520 reg = <0x021d0000 0x4000>;
521 interrupts = <0 108 0x04>;
522 };
523
524 tzasc@021d4000 { /* TZASC2 */
525 reg = <0x021d4000 0x4000>;
526 interrupts = <0 109 0x04>;
527 };
528
529 audmux@021d8000 {
530 reg = <0x021d8000 0x4000>;
531 };
532
533 mipi@021dc000 { /* MIPI-CSI */
534 reg = <0x021dc000 0x4000>;
535 };
536
537 mipi@021e0000 { /* MIPI-DSI */
538 reg = <0x021e0000 0x4000>;
539 };
540
541 vdoa@021e4000 {
542 reg = <0x021e4000 0x4000>;
543 interrupts = <0 18 0x04>;
544 };
545
546 uart1: uart@021e8000 { /* UART2 */
547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
548 reg = <0x021e8000 0x4000>;
549 interrupts = <0 27 0x04>;
550 status = "disabled";
551 };
552
553 uart2: uart@021ec000 { /* UART3 */
554 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
555 reg = <0x021ec000 0x4000>;
556 interrupts = <0 28 0x04>;
557 status = "disabled";
558 };
559
560 uart3: uart@021f0000 { /* UART4 */
561 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
562 reg = <0x021f0000 0x4000>;
563 interrupts = <0 29 0x04>;
564 status = "disabled";
565 };
566
567 uart4: uart@021f4000 { /* UART5 */
568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
569 reg = <0x021f4000 0x4000>;
570 interrupts = <0 30 0x04>;
571 status = "disabled";
572 };
573 };
574 };
575};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
new file mode 100644
index 000000000000..f0a8c2068ea7
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -0,0 +1,249 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X2";
16 compatible = "picochip,pc3x2";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,1176jz-s";
26 clock-frequency = <400000000>;
27 reg = <0>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 pclk: clock@0 {
41 compatible = "fixed-clock";
42 clock-outputs = "bus", "pclk";
43 clock-frequency = <200000000>;
44 ref-clock = <&ref_clk>, "ref";
45 };
46 };
47
48 paxi {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges = <0 0x80000000 0x400000>;
53
54 emac: gem@30000 {
55 compatible = "cadence,gem";
56 reg = <0x30000 0x10000>;
57 interrupts = <31>;
58 };
59
60 dmac1: dmac@40000 {
61 compatible = "snps,dw-dmac";
62 reg = <0x40000 0x10000>;
63 interrupts = <25>;
64 };
65
66 dmac2: dmac@50000 {
67 compatible = "snps,dw-dmac";
68 reg = <0x50000 0x10000>;
69 interrupts = <26>;
70 };
71
72 vic0: interrupt-controller@60000 {
73 compatible = "arm,pl192-vic";
74 interrupt-controller;
75 reg = <0x60000 0x1000>;
76 #interrupt-cells = <1>;
77 };
78
79 vic1: interrupt-controller@64000 {
80 compatible = "arm,pl192-vic";
81 interrupt-controller;
82 reg = <0x64000 0x1000>;
83 #interrupt-cells = <1>;
84 };
85
86 fuse: picoxcell-fuse@80000 {
87 compatible = "picoxcell,fuse-pc3x2";
88 reg = <0x80000 0x10000>;
89 };
90
91 ssi: picoxcell-spi@90000 {
92 compatible = "picoxcell,spi";
93 reg = <0x90000 0x10000>;
94 interrupt-parent = <&vic0>;
95 interrupts = <10>;
96 };
97
98 ipsec: spacc@100000 {
99 compatible = "picochip,spacc-ipsec";
100 reg = <0x100000 0x10000>;
101 interrupt-parent = <&vic0>;
102 interrupts = <24>;
103 ref-clock = <&pclk>, "ref";
104 };
105
106 srtp: spacc@140000 {
107 compatible = "picochip,spacc-srtp";
108 reg = <0x140000 0x10000>;
109 interrupt-parent = <&vic0>;
110 interrupts = <23>;
111 };
112
113 l2_engine: spacc@180000 {
114 compatible = "picochip,spacc-l2";
115 reg = <0x180000 0x10000>;
116 interrupt-parent = <&vic0>;
117 interrupts = <22>;
118 ref-clock = <&pclk>, "ref";
119 };
120
121 apb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x200000 0x80000>;
126
127 rtc0: rtc@00000 {
128 compatible = "picochip,pc3x2-rtc";
129 clock-freq = <200000000>;
130 reg = <0x00000 0xf>;
131 interrupt-parent = <&vic1>;
132 interrupts = <8>;
133 };
134
135 timer0: timer@10000 {
136 compatible = "picochip,pc3x2-timer";
137 interrupt-parent = <&vic0>;
138 interrupts = <4>;
139 clock-freq = <200000000>;
140 reg = <0x10000 0x14>;
141 };
142
143 timer1: timer@10014 {
144 compatible = "picochip,pc3x2-timer";
145 interrupt-parent = <&vic0>;
146 interrupts = <5>;
147 clock-freq = <200000000>;
148 reg = <0x10014 0x14>;
149 };
150
151 timer2: timer@10028 {
152 compatible = "picochip,pc3x2-timer";
153 interrupt-parent = <&vic0>;
154 interrupts = <6>;
155 clock-freq = <200000000>;
156 reg = <0x10028 0x14>;
157 };
158
159 timer3: timer@1003c {
160 compatible = "picochip,pc3x2-timer";
161 interrupt-parent = <&vic0>;
162 interrupts = <7>;
163 clock-freq = <200000000>;
164 reg = <0x1003c 0x14>;
165 };
166
167 gpio: gpio@20000 {
168 compatible = "snps,dw-apb-gpio";
169 reg = <0x20000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg-io-width = <4>;
173
174 banka: gpio-controller@0 {
175 compatible = "snps,dw-apb-gpio-bank";
176 gpio-controller;
177 #gpio-cells = <2>;
178 gpio-generic,nr-gpio = <8>;
179
180 regoffset-dat = <0x50>;
181 regoffset-set = <0x00>;
182 regoffset-dirout = <0x04>;
183 };
184
185 bankb: gpio-controller@1 {
186 compatible = "snps,dw-apb-gpio-bank";
187 gpio-controller;
188 #gpio-cells = <2>;
189 gpio-generic,nr-gpio = <8>;
190
191 regoffset-dat = <0x54>;
192 regoffset-set = <0x0c>;
193 regoffset-dirout = <0x10>;
194 };
195 };
196
197 uart0: uart@30000 {
198 compatible = "snps,dw-apb-uart";
199 reg = <0x30000 0x1000>;
200 interrupt-parent = <&vic1>;
201 interrupts = <10>;
202 clock-frequency = <3686400>;
203 reg-shift = <2>;
204 reg-io-width = <4>;
205 };
206
207 uart1: uart@40000 {
208 compatible = "snps,dw-apb-uart";
209 reg = <0x40000 0x1000>;
210 interrupt-parent = <&vic1>;
211 interrupts = <9>;
212 clock-frequency = <3686400>;
213 reg-shift = <2>;
214 reg-io-width = <4>;
215 };
216
217 wdog: watchdog@50000 {
218 compatible = "snps,dw-apb-wdg";
219 reg = <0x50000 0x10000>;
220 interrupt-parent = <&vic0>;
221 interrupts = <11>;
222 bus-clock = <&pclk>, "bus";
223 };
224 };
225 };
226
227 rwid-axi {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "simple-bus";
231 ranges;
232
233 ebi@50000000 {
234 compatible = "simple-bus";
235 #address-cells = <2>;
236 #size-cells = <1>;
237 ranges = <0 0 0x40000000 0x08000000
238 1 0 0x48000000 0x08000000
239 2 0 0x50000000 0x08000000
240 3 0 0x58000000 0x08000000>;
241 };
242
243 axi2pico@c0000000 {
244 compatible = "picochip,axi2pico-pc3x2";
245 reg = <0xc0000000 0x10000>;
246 interrupts = <13 14 15 16 17 18 19 20 21>;
247 };
248 };
249};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
new file mode 100644
index 000000000000..daa962d191e6
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -0,0 +1,365 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X3";
16 compatible = "picochip,pc3x3";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,1176jz-s";
26 cpu-clock = <&arm_clk>, "cpu";
27 reg = <0>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 clkgate: clkgate@800a0048 {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0x800a0048 4>;
44 compatible = "picochip,pc3x3-clk-gate";
45
46 tzprot_clk: clock@0 {
47 compatible = "picochip,pc3x3-gated-clk";
48 clock-outputs = "bus";
49 picochip,clk-disable-bit = <0>;
50 clock-frequency = <200000000>;
51 ref-clock = <&ref_clk>, "ref";
52 };
53
54 spi_clk: clock@1 {
55 compatible = "picochip,pc3x3-gated-clk";
56 clock-outputs = "bus";
57 picochip,clk-disable-bit = <1>;
58 clock-frequency = <200000000>;
59 ref-clock = <&ref_clk>, "ref";
60 };
61
62 dmac0_clk: clock@2 {
63 compatible = "picochip,pc3x3-gated-clk";
64 clock-outputs = "bus";
65 picochip,clk-disable-bit = <2>;
66 clock-frequency = <200000000>;
67 ref-clock = <&ref_clk>, "ref";
68 };
69
70 dmac1_clk: clock@3 {
71 compatible = "picochip,pc3x3-gated-clk";
72 clock-outputs = "bus";
73 picochip,clk-disable-bit = <3>;
74 clock-frequency = <200000000>;
75 ref-clock = <&ref_clk>, "ref";
76 };
77
78 ebi_clk: clock@4 {
79 compatible = "picochip,pc3x3-gated-clk";
80 clock-outputs = "bus";
81 picochip,clk-disable-bit = <4>;
82 clock-frequency = <200000000>;
83 ref-clock = <&ref_clk>, "ref";
84 };
85
86 ipsec_clk: clock@5 {
87 compatible = "picochip,pc3x3-gated-clk";
88 clock-outputs = "bus";
89 picochip,clk-disable-bit = <5>;
90 clock-frequency = <200000000>;
91 ref-clock = <&ref_clk>, "ref";
92 };
93
94 l2_clk: clock@6 {
95 compatible = "picochip,pc3x3-gated-clk";
96 clock-outputs = "bus";
97 picochip,clk-disable-bit = <6>;
98 clock-frequency = <200000000>;
99 ref-clock = <&ref_clk>, "ref";
100 };
101
102 trng_clk: clock@7 {
103 compatible = "picochip,pc3x3-gated-clk";
104 clock-outputs = "bus";
105 picochip,clk-disable-bit = <7>;
106 clock-frequency = <200000000>;
107 ref-clock = <&ref_clk>, "ref";
108 };
109
110 fuse_clk: clock@8 {
111 compatible = "picochip,pc3x3-gated-clk";
112 clock-outputs = "bus";
113 picochip,clk-disable-bit = <8>;
114 clock-frequency = <200000000>;
115 ref-clock = <&ref_clk>, "ref";
116 };
117
118 otp_clk: clock@9 {
119 compatible = "picochip,pc3x3-gated-clk";
120 clock-outputs = "bus";
121 picochip,clk-disable-bit = <9>;
122 clock-frequency = <200000000>;
123 ref-clock = <&ref_clk>, "ref";
124 };
125 };
126
127 arm_clk: clock@11 {
128 compatible = "picochip,pc3x3-pll";
129 reg = <0x800a0050 0x8>;
130 picochip,min-freq = <140000000>;
131 picochip,max-freq = <700000000>;
132 ref-clock = <&ref_clk>, "ref";
133 clock-outputs = "cpu";
134 };
135
136 pclk: clock@12 {
137 compatible = "fixed-clock";
138 clock-outputs = "bus", "pclk";
139 clock-frequency = <200000000>;
140 ref-clock = <&ref_clk>, "ref";
141 };
142 };
143
144 paxi {
145 compatible = "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges = <0 0x80000000 0x400000>;
149
150 emac: gem@30000 {
151 compatible = "cadence,gem";
152 reg = <0x30000 0x10000>;
153 interrupt-parent = <&vic0>;
154 interrupts = <31>;
155 };
156
157 dmac1: dmac@40000 {
158 compatible = "snps,dw-dmac";
159 reg = <0x40000 0x10000>;
160 interrupt-parent = <&vic0>;
161 interrupts = <25>;
162 };
163
164 dmac2: dmac@50000 {
165 compatible = "snps,dw-dmac";
166 reg = <0x50000 0x10000>;
167 interrupt-parent = <&vic0>;
168 interrupts = <26>;
169 };
170
171 vic0: interrupt-controller@60000 {
172 compatible = "arm,pl192-vic";
173 interrupt-controller;
174 reg = <0x60000 0x1000>;
175 #interrupt-cells = <1>;
176 };
177
178 vic1: interrupt-controller@64000 {
179 compatible = "arm,pl192-vic";
180 interrupt-controller;
181 reg = <0x64000 0x1000>;
182 #interrupt-cells = <1>;
183 };
184
185 fuse: picoxcell-fuse@80000 {
186 compatible = "picoxcell,fuse-pc3x3";
187 reg = <0x80000 0x10000>;
188 };
189
190 ssi: picoxcell-spi@90000 {
191 compatible = "picoxcell,spi";
192 reg = <0x90000 0x10000>;
193 interrupt-parent = <&vic0>;
194 interrupts = <10>;
195 };
196
197 ipsec: spacc@100000 {
198 compatible = "picochip,spacc-ipsec";
199 reg = <0x100000 0x10000>;
200 interrupt-parent = <&vic0>;
201 interrupts = <24>;
202 ref-clock = <&ipsec_clk>, "ref";
203 };
204
205 srtp: spacc@140000 {
206 compatible = "picochip,spacc-srtp";
207 reg = <0x140000 0x10000>;
208 interrupt-parent = <&vic0>;
209 interrupts = <23>;
210 };
211
212 l2_engine: spacc@180000 {
213 compatible = "picochip,spacc-l2";
214 reg = <0x180000 0x10000>;
215 interrupt-parent = <&vic0>;
216 interrupts = <22>;
217 ref-clock = <&l2_clk>, "ref";
218 };
219
220 apb {
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0 0x200000 0x80000>;
225
226 rtc0: rtc@00000 {
227 compatible = "picochip,pc3x2-rtc";
228 clock-freq = <200000000>;
229 reg = <0x00000 0xf>;
230 interrupt-parent = <&vic0>;
231 interrupts = <8>;
232 };
233
234 timer0: timer@10000 {
235 compatible = "picochip,pc3x2-timer";
236 interrupt-parent = <&vic0>;
237 interrupts = <4>;
238 clock-freq = <200000000>;
239 reg = <0x10000 0x14>;
240 };
241
242 timer1: timer@10014 {
243 compatible = "picochip,pc3x2-timer";
244 interrupt-parent = <&vic0>;
245 interrupts = <5>;
246 clock-freq = <200000000>;
247 reg = <0x10014 0x14>;
248 };
249
250 gpio: gpio@20000 {
251 compatible = "snps,dw-apb-gpio";
252 reg = <0x20000 0x1000>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg-io-width = <4>;
256
257 banka: gpio-controller@0 {
258 compatible = "snps,dw-apb-gpio-bank";
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-generic,nr-gpio = <8>;
262
263 regoffset-dat = <0x50>;
264 regoffset-set = <0x00>;
265 regoffset-dirout = <0x04>;
266 };
267
268 bankb: gpio-controller@1 {
269 compatible = "snps,dw-apb-gpio-bank";
270 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-generic,nr-gpio = <16>;
273
274 regoffset-dat = <0x54>;
275 regoffset-set = <0x0c>;
276 regoffset-dirout = <0x10>;
277 };
278
279 bankd: gpio-controller@2 {
280 compatible = "snps,dw-apb-gpio-bank";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-generic,nr-gpio = <30>;
284
285 regoffset-dat = <0x5c>;
286 regoffset-set = <0x24>;
287 regoffset-dirout = <0x28>;
288 };
289 };
290
291 uart0: uart@30000 {
292 compatible = "snps,dw-apb-uart";
293 reg = <0x30000 0x1000>;
294 interrupt-parent = <&vic1>;
295 interrupts = <10>;
296 clock-frequency = <3686400>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
299 };
300
301 uart1: uart@40000 {
302 compatible = "snps,dw-apb-uart";
303 reg = <0x40000 0x1000>;
304 interrupt-parent = <&vic1>;
305 interrupts = <9>;
306 clock-frequency = <3686400>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 };
310
311 wdog: watchdog@50000 {
312 compatible = "snps,dw-apb-wdg";
313 reg = <0x50000 0x10000>;
314 interrupt-parent = <&vic0>;
315 interrupts = <11>;
316 bus-clock = <&pclk>, "bus";
317 };
318
319 timer2: timer@60000 {
320 compatible = "picochip,pc3x2-timer";
321 interrupt-parent = <&vic0>;
322 interrupts = <6>;
323 clock-freq = <200000000>;
324 reg = <0x60000 0x14>;
325 };
326
327 timer3: timer@60014 {
328 compatible = "picochip,pc3x2-timer";
329 interrupt-parent = <&vic0>;
330 interrupts = <7>;
331 clock-freq = <200000000>;
332 reg = <0x60014 0x14>;
333 };
334 };
335 };
336
337 rwid-axi {
338 #address-cells = <1>;
339 #size-cells = <1>;
340 compatible = "simple-bus";
341 ranges;
342
343 ebi@50000000 {
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <1>;
347 ranges = <0 0 0x40000000 0x08000000
348 1 0 0x48000000 0x08000000
349 2 0 0x50000000 0x08000000
350 3 0 0x58000000 0x08000000>;
351 };
352
353 axi2pico@c0000000 {
354 compatible = "picochip,axi2pico-pc3x3";
355 reg = <0xc0000000 0x10000>;
356 interrupt-parent = <&vic0>;
357 interrupts = <13 14 15 16 17 18 19 20 21>;
358 };
359
360 otp@ffff8000 {
361 compatible = "picochip,otp-pc3x3";
362 reg = <0xffff8000 0x8000>;
363 };
364 };
365};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
new file mode 100644
index 000000000000..1297414dd649
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
@@ -0,0 +1,86 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/include/ "picoxcell-pc3x2.dtsi"
16/ {
17 model = "Picochip PC7302 (PC3X2)";
18 compatible = "picochip,pc7302-pc3x2", "picochip,pc3x2";
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x08000000>;
23 };
24
25 chosen {
26 linux,stdout-path = &uart0;
27 };
28
29 clocks {
30 ref_clk: clock@1 {
31 compatible = "fixed-clock";
32 clock-outputs = "ref";
33 clock-frequency = <20000000>;
34 };
35 };
36
37 rwid-axi {
38 ebi@50000000 {
39 nand: gpio-nand@2,0 {
40 compatible = "gpio-control-nand";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 reg = <2 0x0000 0x1000>;
44 bus-clock = <&pclk>, "bus";
45 gpio-control-nand,io-sync-reg =
46 <0x00000000 0x80220000>;
47
48 gpios = <&banka 1 0 /* rdy */
49 &banka 2 0 /* nce */
50 &banka 3 0 /* ale */
51 &banka 4 0 /* cle */
52 0 /* nwp */>;
53
54 boot@100000 {
55 label = "Boot";
56 reg = <0x100000 0x80000>;
57 };
58
59 redundant-boot@200000 {
60 label = "Redundant Boot";
61 reg = <0x200000 0x80000>;
62 };
63
64 boot-env@300000 {
65 label = "Boot Evironment";
66 reg = <0x300000 0x20000>;
67 };
68
69 redundant-boot-env@320000 {
70 label = "Redundant Boot Environment";
71 reg = <0x300000 0x20000>;
72 };
73
74 kernel@380000 {
75 label = "Kernel";
76 reg = <0x380000 0x800000>;
77 };
78
79 fs@b80000 {
80 label = "File System";
81 reg = <0xb80000 0xf480000>;
82 };
83 };
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
new file mode 100644
index 000000000000..9e317a4f431c
--- /dev/null
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
@@ -0,0 +1,92 @@
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15/include/ "picoxcell-pc3x3.dtsi"
16/ {
17 model = "Picochip PC7302 (PC3X3)";
18 compatible = "picochip,pc7302-pc3x3", "picochip,pc3x3";
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x08000000>;
23 };
24
25 chosen {
26 linux,stdout-path = &uart0;
27 };
28
29 clocks {
30 ref_clk: clock@10 {
31 compatible = "fixed-clock";
32 clock-outputs = "ref";
33 clock-frequency = <20000000>;
34 };
35
36 clkgate: clkgate@800a0048 {
37 clock@4 {
38 picochip,clk-no-disable;
39 };
40 };
41 };
42
43 rwid-axi {
44 ebi@50000000 {
45 nand: gpio-nand@2,0 {
46 compatible = "gpio-control-nand";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <2 0x0000 0x1000>;
50 bus-clock = <&ebi_clk>, "bus";
51 gpio-control-nand,io-sync-reg =
52 <0x00000000 0x80220000>;
53
54 gpios = <&banka 1 0 /* rdy */
55 &banka 2 0 /* nce */
56 &banka 3 0 /* ale */
57 &banka 4 0 /* cle */
58 0 /* nwp */>;
59
60 boot@100000 {
61 label = "Boot";
62 reg = <0x100000 0x80000>;
63 };
64
65 redundant-boot@200000 {
66 label = "Redundant Boot";
67 reg = <0x200000 0x80000>;
68 };
69
70 boot-env@300000 {
71 label = "Boot Evironment";
72 reg = <0x300000 0x20000>;
73 };
74
75 redundant-boot-env@320000 {
76 label = "Redundant Boot Environment";
77 reg = <0x300000 0x20000>;
78 };
79
80 kernel@380000 {
81 label = "Kernel";
82 reg = <0x380000 0x800000>;
83 };
84
85 fs@b80000 {
86 label = "File System";
87 reg = <0xb80000 0xf480000>;
88 };
89 };
90 };
91 };
92};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 11:23:59 -0400