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authorLinus Torvalds <torvalds@g5.osdl.org>2006-03-25 23:29:54 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-25 23:29:54 -0500
commita41622eaa97e40c811fb7756f403c0d4caa65654 (patch)
tree43dc2d74f80fc18d0467dcd2fe2168b2fccb845d /arch/arm/boot
parent0b5c59a1e41636afa77b90d34e8c394d8d929733 (diff)
parent2ce9804fbd9d4da75fb5bb53331b46b614a7d5c3 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3030/2: fix permission check in the obscur cmpxchg syscall [ARM] nommu: rename compressed/head.S symbols to a new style [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h [ARM] Move read of processor ID out of lookup_processor_type() [ARM] Fix typo in tlbflush.h [ARM] noMMU: removes TLB codes in nommu mode [ARM] noMMU: block sys_fork in nommu mode [ARM] 3399/1: Fix link problem when CONFIG_PRINTK is disabled [ARM] 3398/1: Fix the VFP registers loading/storing base address [ARM] 3397/1: AT91RM9200 Header update [ARM] 3385/1: Battery support for sharp zaurus sl-5500 (collie) [ARM] SMP: don't set cpu_*_map in smp_prepare_boot_cpu include/linux/clk.h is betraying its ARM origins [ARM] Move enable_irq and disable_irq to assembler.h [ARM] 3391/1: use PLAT8250_DEV_PLATFORM{,1} for platform device id instead of 0/1
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/compressed/head.S82
1 files changed, 41 insertions, 41 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index db3389d8e027..491c7e4c9ac6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -358,7 +358,7 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
358 str r1, [r0] 358 str r1, [r0]
359 mov pc, lr 359 mov pc, lr
360 360
361__armv4_cache_on: 361__armv4_mmu_cache_on:
362 mov r12, lr 362 mov r12, lr
363 bl __setup_mmu 363 bl __setup_mmu
364 mov r0, #0 364 mov r0, #0
@@ -367,24 +367,24 @@ __armv4_cache_on:
367 mrc p15, 0, r0, c1, c0, 0 @ read control reg 367 mrc p15, 0, r0, c1, c0, 0 @ read control reg
368 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 368 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
369 orr r0, r0, #0x0030 369 orr r0, r0, #0x0030
370 bl __common_cache_on 370 bl __common_mmu_cache_on
371 mov r0, #0 371 mov r0, #0
372 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 372 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
373 mov pc, r12 373 mov pc, r12
374 374
375__arm6_cache_on: 375__arm6_mmu_cache_on:
376 mov r12, lr 376 mov r12, lr
377 bl __setup_mmu 377 bl __setup_mmu
378 mov r0, #0 378 mov r0, #0
379 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 379 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
380 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 380 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
381 mov r0, #0x30 381 mov r0, #0x30
382 bl __common_cache_on 382 bl __common_mmu_cache_on
383 mov r0, #0 383 mov r0, #0
384 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 384 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
385 mov pc, r12 385 mov pc, r12
386 386
387__common_cache_on: 387__common_mmu_cache_on:
388#ifndef DEBUG 388#ifndef DEBUG
389 orr r0, r0, #0x000d @ Write buffer, mmu 389 orr r0, r0, #0x000d @ Write buffer, mmu
390#endif 390#endif
@@ -471,12 +471,12 @@ call_cache_fn: adr r12, proc_types
471proc_types: 471proc_types:
472 .word 0x41560600 @ ARM6/610 472 .word 0x41560600 @ ARM6/610
473 .word 0xffffffe0 473 .word 0xffffffe0
474 b __arm6_cache_off @ works, but slow 474 b __arm6_mmu_cache_off @ works, but slow
475 b __arm6_cache_off 475 b __arm6_mmu_cache_off
476 mov pc, lr 476 mov pc, lr
477@ b __arm6_cache_on @ untested 477@ b __arm6_mmu_cache_on @ untested
478@ b __arm6_cache_off 478@ b __arm6_mmu_cache_off
479@ b __armv3_cache_flush 479@ b __armv3_mmu_cache_flush
480 480
481 .word 0x00000000 @ old ARM ID 481 .word 0x00000000 @ old ARM ID
482 .word 0x0000f000 482 .word 0x0000f000
@@ -486,14 +486,14 @@ proc_types:
486 486
487 .word 0x41007000 @ ARM7/710 487 .word 0x41007000 @ ARM7/710
488 .word 0xfff8fe00 488 .word 0xfff8fe00
489 b __arm7_cache_off 489 b __arm7_mmu_cache_off
490 b __arm7_cache_off 490 b __arm7_mmu_cache_off
491 mov pc, lr 491 mov pc, lr
492 492
493 .word 0x41807200 @ ARM720T (writethrough) 493 .word 0x41807200 @ ARM720T (writethrough)
494 .word 0xffffff00 494 .word 0xffffff00
495 b __armv4_cache_on 495 b __armv4_mmu_cache_on
496 b __armv4_cache_off 496 b __armv4_mmu_cache_off
497 mov pc, lr 497 mov pc, lr
498 498
499 .word 0x00007000 @ ARM7 IDs 499 .word 0x00007000 @ ARM7 IDs
@@ -506,41 +506,41 @@ proc_types:
506 506
507 .word 0x4401a100 @ sa110 / sa1100 507 .word 0x4401a100 @ sa110 / sa1100
508 .word 0xffffffe0 508 .word 0xffffffe0
509 b __armv4_cache_on 509 b __armv4_mmu_cache_on
510 b __armv4_cache_off 510 b __armv4_mmu_cache_off
511 b __armv4_cache_flush 511 b __armv4_mmu_cache_flush
512 512
513 .word 0x6901b110 @ sa1110 513 .word 0x6901b110 @ sa1110
514 .word 0xfffffff0 514 .word 0xfffffff0
515 b __armv4_cache_on 515 b __armv4_mmu_cache_on
516 b __armv4_cache_off 516 b __armv4_mmu_cache_off
517 b __armv4_cache_flush 517 b __armv4_mmu_cache_flush
518 518
519 @ These match on the architecture ID 519 @ These match on the architecture ID
520 520
521 .word 0x00020000 @ ARMv4T 521 .word 0x00020000 @ ARMv4T
522 .word 0x000f0000 522 .word 0x000f0000
523 b __armv4_cache_on 523 b __armv4_mmu_cache_on
524 b __armv4_cache_off 524 b __armv4_mmu_cache_off
525 b __armv4_cache_flush 525 b __armv4_mmu_cache_flush
526 526
527 .word 0x00050000 @ ARMv5TE 527 .word 0x00050000 @ ARMv5TE
528 .word 0x000f0000 528 .word 0x000f0000
529 b __armv4_cache_on 529 b __armv4_mmu_cache_on
530 b __armv4_cache_off 530 b __armv4_mmu_cache_off
531 b __armv4_cache_flush 531 b __armv4_mmu_cache_flush
532 532
533 .word 0x00060000 @ ARMv5TEJ 533 .word 0x00060000 @ ARMv5TEJ
534 .word 0x000f0000 534 .word 0x000f0000
535 b __armv4_cache_on 535 b __armv4_mmu_cache_on
536 b __armv4_cache_off 536 b __armv4_mmu_cache_off
537 b __armv4_cache_flush 537 b __armv4_mmu_cache_flush
538 538
539 .word 0x00070000 @ ARMv6 539 .word 0x00070000 @ ARMv6
540 .word 0x000f0000 540 .word 0x000f0000
541 b __armv4_cache_on 541 b __armv4_mmu_cache_on
542 b __armv4_cache_off 542 b __armv4_mmu_cache_off
543 b __armv6_cache_flush 543 b __armv6_mmu_cache_flush
544 544
545 .word 0 @ unrecognised type 545 .word 0 @ unrecognised type
546 .word 0 546 .word 0
@@ -562,7 +562,7 @@ proc_types:
562cache_off: mov r3, #12 @ cache_off function 562cache_off: mov r3, #12 @ cache_off function
563 b call_cache_fn 563 b call_cache_fn
564 564
565__armv4_cache_off: 565__armv4_mmu_cache_off:
566 mrc p15, 0, r0, c1, c0 566 mrc p15, 0, r0, c1, c0
567 bic r0, r0, #0x000d 567 bic r0, r0, #0x000d
568 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 568 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
@@ -571,15 +571,15 @@ __armv4_cache_off:
571 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 571 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
572 mov pc, lr 572 mov pc, lr
573 573
574__arm6_cache_off: 574__arm6_mmu_cache_off:
575 mov r0, #0x00000030 @ ARM6 control reg. 575 mov r0, #0x00000030 @ ARM6 control reg.
576 b __armv3_cache_off 576 b __armv3_mmu_cache_off
577 577
578__arm7_cache_off: 578__arm7_mmu_cache_off:
579 mov r0, #0x00000070 @ ARM7 control reg. 579 mov r0, #0x00000070 @ ARM7 control reg.
580 b __armv3_cache_off 580 b __armv3_mmu_cache_off
581 581
582__armv3_cache_off: 582__armv3_mmu_cache_off:
583 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 583 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
584 mov r0, #0 584 mov r0, #0
585 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 585 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
@@ -601,7 +601,7 @@ cache_clean_flush:
601 mov r3, #16 601 mov r3, #16
602 b call_cache_fn 602 b call_cache_fn
603 603
604__armv6_cache_flush: 604__armv6_mmu_cache_flush:
605 mov r1, #0 605 mov r1, #0
606 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 606 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
607 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 607 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
@@ -609,7 +609,7 @@ __armv6_cache_flush:
609 mcr p15, 0, r1, c7, c10, 4 @ drain WB 609 mcr p15, 0, r1, c7, c10, 4 @ drain WB
610 mov pc, lr 610 mov pc, lr
611 611
612__armv4_cache_flush: 612__armv4_mmu_cache_flush:
613 mov r2, #64*1024 @ default: 32K dcache size (*2) 613 mov r2, #64*1024 @ default: 32K dcache size (*2)
614 mov r11, #32 @ default: 32 byte line size 614 mov r11, #32 @ default: 32 byte line size
615 mrc p15, 0, r3, c0, c0, 1 @ read cache type 615 mrc p15, 0, r3, c0, c0, 1 @ read cache type
@@ -637,7 +637,7 @@ no_cache_id:
637 mcr p15, 0, r1, c7, c10, 4 @ drain WB 637 mcr p15, 0, r1, c7, c10, 4 @ drain WB
638 mov pc, lr 638 mov pc, lr
639 639
640__armv3_cache_flush: 640__armv3_mmu_cache_flush:
641 mov r1, #0 641 mov r1, #0
642 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 642 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
643 mov pc, lr 643 mov pc, lr