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authorMichal Simek <michal.simek@xilinx.com>2013-03-20 05:15:28 -0400
committerMichal Simek <michal.simek@xilinx.com>2013-04-04 03:09:08 -0400
commite932900a3279b5dbb6d8f43c7b369003620e137c (patch)
tree9278ee3e2b6f951a72ef5479029f836403950a11 /arch/arm/boot/dts/zynq-7000.dtsi
parent3d5a96582303e28c48699f3faaf920ef7d43e6f2 (diff)
arm: zynq: Use standard timer binding
Use cdns,ttc because this driver is Cadence Rev06 Triple Timer Counter and everybody can use it without xilinx specific function name or probing. Also use standard dt description for timer and also prepare for moving to clocksource initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/boot/dts/zynq-7000.dtsi')
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi45
1 files changed, 6 insertions, 39 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5914b5654591..51243db2e9e4 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -111,56 +111,23 @@
111 }; 111 };
112 112
113 ttc0: ttc0@f8001000 { 113 ttc0: ttc0@f8001000 {
114 #address-cells = <1>; 114 interrupt-parent = <&intc>;
115 #size-cells = <0>; 115 interrupts = < 0 10 4 0 11 4 0 12 4 >;
116 compatible = "xlnx,ttc"; 116 compatible = "cdns,ttc";
117 reg = <0xF8001000 0x1000>; 117 reg = <0xF8001000 0x1000>;
118 clocks = <&cpu_clk 3>; 118 clocks = <&cpu_clk 3>;
119 clock-names = "cpu_1x"; 119 clock-names = "cpu_1x";
120 clock-ranges; 120 clock-ranges;
121
122 ttc0_0: ttc0.0 {
123 status = "disabled";
124 reg = <0>;
125 interrupts = <0 10 4>;
126 };
127 ttc0_1: ttc0.1 {
128 status = "disabled";
129 reg = <1>;
130 interrupts = <0 11 4>;
131 };
132 ttc0_2: ttc0.2 {
133 status = "disabled";
134 reg = <2>;
135 interrupts = <0 12 4>;
136 };
137 }; 121 };
138 122
139 ttc1: ttc1@f8002000 { 123 ttc1: ttc1@f8002000 {
140 #interrupt-parent = <&intc>; 124 interrupt-parent = <&intc>;
141 #address-cells = <1>; 125 interrupts = < 0 37 4 0 38 4 0 39 4 >;
142 #size-cells = <0>; 126 compatible = "cdns,ttc";
143 compatible = "xlnx,ttc";
144 reg = <0xF8002000 0x1000>; 127 reg = <0xF8002000 0x1000>;
145 clocks = <&cpu_clk 3>; 128 clocks = <&cpu_clk 3>;
146 clock-names = "cpu_1x"; 129 clock-names = "cpu_1x";
147 clock-ranges; 130 clock-ranges;
148
149 ttc1_0: ttc1.0 {
150 status = "disabled";
151 reg = <0>;
152 interrupts = <0 37 4>;
153 };
154 ttc1_1: ttc1.1 {
155 status = "disabled";
156 reg = <1>;
157 interrupts = <0 38 4>;
158 };
159 ttc1_2: ttc1.2 {
160 status = "disabled";
161 reg = <2>;
162 interrupts = <0 39 4>;
163 };
164 }; 131 };
165 }; 132 };
166}; 133};