dts: vt8500: Correct reference clock on WM8850 SoCs

WM8850 SoCs use a 24Mhz reference clock for the PLLs but the SoC file
currently parents all PLLs to the 25Mhz reference clock.

This patch corrects the PLL parent clock references.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>

1 files changed, 7 insertions, 7 deletions

diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index 1f49f54c38d2..d98386dd2882 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -84,49 +84,49 @@
                                 plla: plla {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x200>;
                                 };
 
                                 pllb: pllb {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x204>;
                                 };
 
                                 pllc: pllc {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x208>;
                                 };
 
                                 plld: plld {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x20c>;
                                 };
 
                                 plle: plle {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x210>;
                                 };
 
                                 pllf: pllf {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x214>;
                                 };
 
                                 pllg: pllg {
                                         #clock-cells = <0>;
                                         compatible = "wm,wm8850-pll-clock";
-                                        clocks = <&ref25>;
+                                        clocks = <&ref24>;
                                         reg = <0x218>;
                                 };