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authorShawn Guo <shawn.guo@linaro.org>2013-07-10 02:05:44 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-07-14 20:28:09 -0400
commit4f71612ee3a1b2d15c8246d926a40c4f7d21cc3b (patch)
treef908b3bf73633398dc54450dac3f9dd513344f69 /arch/arm/boot/dts/vf610.dtsi
parent66acaf3f897c9245f5456d884e5ae401700cbc45 (diff)
ARM: imx: fix vf610 enet module clock selection
The fec/enet driver calculates MDC rate with the formula below. ref_freq / ((MII_SPEED + 1) x 2) The ref_freq here is the fec internal module clock, which is missing from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly supplies RMII clock (50 MHz) as the source to fec. This results in the situation that fec driver gets ref_freq as 50 MHz, while physically it runs at 66 MHz (fec module clock physically sources from ipg which runs at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041 keeps swithing between Full and Half mode as below. libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half Add the missing module clock for ENET0 and ENET1, and correct the clock supplying in device tree to fix above issue. Thanks to Alison Wang <b18965@freescale.com> for debugging the issue. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/vf610.dtsi')
-rw-r--r--arch/arm/boot/dts/vf610.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index e1eb7dadda80..67d929cf9804 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -442,8 +442,8 @@
442 compatible = "fsl,mvf600-fec"; 442 compatible = "fsl,mvf600-fec";
443 reg = <0x400d0000 0x1000>; 443 reg = <0x400d0000 0x1000>;
444 interrupts = <0 78 0x04>; 444 interrupts = <0 78 0x04>;
445 clocks = <&clks VF610_CLK_ENET>, 445 clocks = <&clks VF610_CLK_ENET0>,
446 <&clks VF610_CLK_ENET>, 446 <&clks VF610_CLK_ENET0>,
447 <&clks VF610_CLK_ENET>; 447 <&clks VF610_CLK_ENET>;
448 clock-names = "ipg", "ahb", "ptp"; 448 clock-names = "ipg", "ahb", "ptp";
449 status = "disabled"; 449 status = "disabled";
@@ -453,8 +453,8 @@
453 compatible = "fsl,mvf600-fec"; 453 compatible = "fsl,mvf600-fec";
454 reg = <0x400d1000 0x1000>; 454 reg = <0x400d1000 0x1000>;
455 interrupts = <0 79 0x04>; 455 interrupts = <0 79 0x04>;
456 clocks = <&clks VF610_CLK_ENET>, 456 clocks = <&clks VF610_CLK_ENET1>,
457 <&clks VF610_CLK_ENET>, 457 <&clks VF610_CLK_ENET1>,
458 <&clks VF610_CLK_ENET>; 458 <&clks VF610_CLK_ENET>;
459 clock-names = "ipg", "ahb", "ptp"; 459 clock-names = "ipg", "ahb", "ptp";
460 status = "disabled"; 460 status = "disabled";