Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC updates from Olof Johansson:
 "This contains the bulk of new SoC development for this merge window.

  Two new platforms have been added, the sunxi platforms (Allwinner A1x
  SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
  series of ARMv7 platforms from them, where the hope is that we can
  keep the platform code generic enough to have them all share one mach
  directory.  The new Broadcom platform is contributed by Christian
  Daudt.

  Highbank has grown support for Calxeda's next generation of hardware,
  ECX-2000.

  clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
  also taken on maintainership of the platform.

  Beyond this there has been a bunch of work from a number of people on
  converting more platforms to IRQ domains, pinctrl conversion, cleanup
  and general feature enablement across most of the active platforms."

Fix up trivial conflicts as per Olof.

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
  mfd: vexpress-sysreg: Remove LEDs code
  irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
  clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
  irq: versatile: delete dangling variable
  ARM: sunxi: add missing include for mdelay()
  ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
  ARM: dts: add node for PL330 MDMA1 controller for exynos4
  ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
  ARM: EXYNOS: add UART3 to DEBUG_LL ports
  ARM: S3C24XX: Add clkdev entry for camif-upll clock
  ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
  ARM: sunxi: Add missing sun4i.dtsi file
  pinctrl: samsung: Do not initialise statics to 0
  ARM i.MX6: remove gate_mask from pllv3
  ARM i.MX6: Fix ethernet PLL clocks
  ARM i.MX6: rename PLLs according to datasheet
  ARM i.MX6: Add pwm support
  ARM i.MX51: Add pwm support
  ARM i.MX53: Add pwm support
  ARM: mx5: Replace clk_register_clkdev with clock DT lookup
  ...

1 files changed, 137 insertions, 9 deletions

diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827bd2bf3..ac870fb3fa0d 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -17,17 +17,16 @@
  * CHANGES TO vexpress-v2m.dtsi!
  */
 
-/ {
-        aliases {
-                arm,v2m_timer = &v2m_timer01;
-        };
-
         motherboard {
-                compatible = "simple-bus";
+                model = "V2M-P1";
+                arm,hbi = <0x190>;
+                arm,vexpress,site = <0>;
                 arm,v2m-memory-map = "rs1";
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                 #address-cells = <2>; /* SMB chipselect number and offset */
                 #size-cells = <1>;
                 #interrupt-cells = <1>;
+                ranges;
 
                 flash@0,00000000 {
                         compatible = "arm,vexpress-flash", "cfi-flash";
@@ -72,14 +71,20 @@
                         #size-cells = <1>;
                         ranges = <0 3 0 0x200000>;
 
-                        sysreg@010000 {
+                        v2m_sysreg: sysreg@010000 {
                                 compatible = "arm,vexpress-sysreg";
                                 reg = <0x010000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                         };
 
-                        sysctl@020000 {
+                        v2m_sysctl: sysctl@020000 {
                                 compatible = "arm,sp810", "arm,primecell";
                                 reg = <0x020000 0x1000>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+                                clock-names = "refclk", "timclk", "apb_pclk";
+                                #clock-cells = <1>;
+                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
                         };
 
                         /* PCI-E I2C bus */
@@ -100,66 +105,92 @@
                                 compatible = "arm,pl041", "arm,primecell";
                                 reg = <0x040000 0x1000>;
                                 interrupts = <11>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                         };
 
                         mmci@050000 {
                                 compatible = "arm,pl180", "arm,primecell";
                                 reg = <0x050000 0x1000>;
                                 interrupts = <9 10>;
+                                cd-gpios = <&v2m_sysreg 0 0>;
+                                wp-gpios = <&v2m_sysreg 1 0>;
+                                max-frequency = <12000000>;
+                                vmmc-supply = <&v2m_fixed_3v3>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "mclk", "apb_pclk";
                         };
 
                         kmi@060000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x060000 0x1000>;
                                 interrupts = <12>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
                         kmi@070000 {
                                 compatible = "arm,pl050", "arm,primecell";
                                 reg = <0x070000 0x1000>;
                                 interrupts = <13>;
+                                clocks = <&v2m_clk24mhz>, <&smbclk>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
                         };
 
                         v2m_serial0: uart@090000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x090000 0x1000>;
                                 interrupts = <5>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial1: uart@0a0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0a0000 0x1000>;
                                 interrupts = <6>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial2: uart@0b0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0b0000 0x1000>;
                                 interrupts = <7>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         v2m_serial3: uart@0c0000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x0c0000 0x1000>;
                                 interrupts = <8>;
+                                clocks = <&v2m_oscclk2>, <&smbclk>;
+                                clock-names = "uartclk", "apb_pclk";
                         };
 
                         wdt@0f0000 {
                                 compatible = "arm,sp805", "arm,primecell";
                                 reg = <0x0f0000 0x1000>;
                                 interrupts = <0>;
+                                clocks = <&v2m_refclk32khz>, <&smbclk>;
+                                clock-names = "wdogclk", "apb_pclk";
                         };
 
                         v2m_timer01: timer@110000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x110000 0x1000>;
                                 interrupts = <2>;
+                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                         };
 
                         v2m_timer23: timer@120000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x120000 0x1000>;
                                 interrupts = <3>;
+                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
                         };
 
                         /* DVI I2C bus */
@@ -185,6 +216,8 @@
                                 compatible = "arm,pl031", "arm,primecell";
                                 reg = <0x170000 0x1000>;
                                 interrupts = <4>;
+                                clocks = <&smbclk>;
+                                clock-names = "apb_pclk";
                         };
 
                         compact-flash@1a0000 {
@@ -198,6 +231,8 @@
                                 compatible = "arm,pl111", "arm,primecell";
                                 reg = <0x1f0000 0x1000>;
                                 interrupts = <14>;
+                                clocks = <&v2m_oscclk1>, <&smbclk>;
+                                clock-names = "clcdclk", "apb_pclk";
                         };
                 };
 
@@ -208,5 +243,98 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+
+                mcc {
+                        compatible = "arm,vexpress,config-bus";
+                        arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                        osc@0 {
+                                /* MCC static memory clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 0>;
+                                freq-range = <25000000 60000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk0";
+                        };
+
+                        v2m_oscclk1: osc@1 {
+                                /* CLCD clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 1>;
+                                freq-range = <23750000 63500000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk1";
+                        };
+
+                        v2m_oscclk2: osc@2 {
+                                /* IO FPGA peripheral clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 2>;
+                                freq-range = <24000000 24000000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk2";
+                        };
+
+                        volt@0 {
+                                /* Logic level voltage */
+                                compatible = "arm,vexpress-volt";
+                                arm,vexpress-sysreg,func = <2 0>;
+                                regulator-name = "VIO";
+                                regulator-always-on;
+                                label = "VIO";
+                        };
+
+                        temp@0 {
+                                /* MCC internal operating temperature */
+                                compatible = "arm,vexpress-temp";
+                                arm,vexpress-sysreg,func = <4 0>;
+                                label = "MCC";
+                        };
+
+                        reset@0 {
+                                compatible = "arm,vexpress-reset";
+                                arm,vexpress-sysreg,func = <5 0>;
+                        };
+
+                        muxfpga@0 {
+                                compatible = "arm,vexpress-muxfpga";
+                                arm,vexpress-sysreg,func = <7 0>;
+                        };
+
+                        shutdown@0 {
+                                compatible = "arm,vexpress-shutdown";
+                                arm,vexpress-sysreg,func = <8 0>;
+                        };
+
+                        reboot@0 {
+                                compatible = "arm,vexpress-reboot";
+                                arm,vexpress-sysreg,func = <9 0>;
+                        };
+
+                        dvimode@0 {
+                                compatible = "arm,vexpress-dvimode";
+                                arm,vexpress-sysreg,func = <11 0>;
+                        };
+                };
         };
-};