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authorStephen Warren <swarren@nvidia.com>2012-05-11 19:32:56 -0400
committerStephen Warren <swarren@nvidia.com>2012-05-14 12:55:23 -0400
commit2a5fdc9adde8476751b63a795e3d66ae2ee3979d (patch)
tree6321e80d6c925469d94e09eab6f13b68dc9d963f /arch/arm/boot/dts/tegra30.dtsi
parent2eaab06ea6cc2d686fd1a6de62b1094bedc4cfca (diff)
ARM: dt: tegra: invert status=disable vs status=okay
In tegra*.dtsi, set status="disable" for all HW modules that the board design may choose not to use. Update all boards to specifically enable any of those modules that are useful by setting status="okay". This makes board files say which features they do use, rather than which they don't, which feels more logical. It also makes the .dts files slightly smaller, at least for existing content. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 5a1c85fbf0f0..2dcc09e784b5 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -82,6 +82,7 @@
82 reg = <0x70006000 0x40>; 82 reg = <0x70006000 0x40>;
83 reg-shift = <2>; 83 reg-shift = <2>;
84 interrupts = <0 36 0x04>; 84 interrupts = <0 36 0x04>;
85 status = "disable";
85 }; 86 };
86 87
87 serial@70006040 { 88 serial@70006040 {
@@ -89,6 +90,7 @@
89 reg = <0x70006040 0x40>; 90 reg = <0x70006040 0x40>;
90 reg-shift = <2>; 91 reg-shift = <2>;
91 interrupts = <0 37 0x04>; 92 interrupts = <0 37 0x04>;
93 status = "disable";
92 }; 94 };
93 95
94 serial@70006200 { 96 serial@70006200 {
@@ -96,6 +98,7 @@
96 reg = <0x70006200 0x100>; 98 reg = <0x70006200 0x100>;
97 reg-shift = <2>; 99 reg-shift = <2>;
98 interrupts = <0 46 0x04>; 100 interrupts = <0 46 0x04>;
101 status = "disable";
99 }; 102 };
100 103
101 serial@70006300 { 104 serial@70006300 {
@@ -103,6 +106,7 @@
103 reg = <0x70006300 0x100>; 106 reg = <0x70006300 0x100>;
104 reg-shift = <2>; 107 reg-shift = <2>;
105 interrupts = <0 90 0x04>; 108 interrupts = <0 90 0x04>;
109 status = "disable";
106 }; 110 };
107 111
108 serial@70006400 { 112 serial@70006400 {
@@ -110,6 +114,7 @@
110 reg = <0x70006400 0x100>; 114 reg = <0x70006400 0x100>;
111 reg-shift = <2>; 115 reg-shift = <2>;
112 interrupts = <0 91 0x04>; 116 interrupts = <0 91 0x04>;
117 status = "disable";
113 }; 118 };
114 119
115 i2c@7000c000 { 120 i2c@7000c000 {
@@ -118,6 +123,7 @@
118 interrupts = <0 38 0x04>; 123 interrupts = <0 38 0x04>;
119 #address-cells = <1>; 124 #address-cells = <1>;
120 #size-cells = <0>; 125 #size-cells = <0>;
126 status = "disable";
121 }; 127 };
122 128
123 i2c@7000c400 { 129 i2c@7000c400 {
@@ -126,6 +132,7 @@
126 interrupts = <0 84 0x04>; 132 interrupts = <0 84 0x04>;
127 #address-cells = <1>; 133 #address-cells = <1>;
128 #size-cells = <0>; 134 #size-cells = <0>;
135 status = "disable";
129 }; 136 };
130 137
131 i2c@7000c500 { 138 i2c@7000c500 {
@@ -134,6 +141,7 @@
134 interrupts = <0 92 0x04>; 141 interrupts = <0 92 0x04>;
135 #address-cells = <1>; 142 #address-cells = <1>;
136 #size-cells = <0>; 143 #size-cells = <0>;
144 status = "disable";
137 }; 145 };
138 146
139 i2c@7000c700 { 147 i2c@7000c700 {
@@ -142,6 +150,7 @@
142 interrupts = <0 120 0x04>; 150 interrupts = <0 120 0x04>;
143 #address-cells = <1>; 151 #address-cells = <1>;
144 #size-cells = <0>; 152 #size-cells = <0>;
153 status = "disable";
145 }; 154 };
146 155
147 i2c@7000d000 { 156 i2c@7000d000 {
@@ -150,6 +159,7 @@
150 interrupts = <0 53 0x04>; 159 interrupts = <0 53 0x04>;
151 #address-cells = <1>; 160 #address-cells = <1>;
152 #size-cells = <0>; 161 #size-cells = <0>;
162 status = "disable";
153 }; 163 };
154 164
155 pmc { 165 pmc {
@@ -191,30 +201,35 @@
191 compatible = "nvidia,tegra30-i2s"; 201 compatible = "nvidia,tegra30-i2s";
192 reg = <0x70080300 0x100>; 202 reg = <0x70080300 0x100>;
193 nvidia,ahub-cif-ids = <4 4>; 203 nvidia,ahub-cif-ids = <4 4>;
204 status = "disable";
194 }; 205 };
195 206
196 tegra_i2s1: i2s@70080400 { 207 tegra_i2s1: i2s@70080400 {
197 compatible = "nvidia,tegra30-i2s"; 208 compatible = "nvidia,tegra30-i2s";
198 reg = <0x70080400 0x100>; 209 reg = <0x70080400 0x100>;
199 nvidia,ahub-cif-ids = <5 5>; 210 nvidia,ahub-cif-ids = <5 5>;
211 status = "disable";
200 }; 212 };
201 213
202 tegra_i2s2: i2s@70080500 { 214 tegra_i2s2: i2s@70080500 {
203 compatible = "nvidia,tegra30-i2s"; 215 compatible = "nvidia,tegra30-i2s";
204 reg = <0x70080500 0x100>; 216 reg = <0x70080500 0x100>;
205 nvidia,ahub-cif-ids = <6 6>; 217 nvidia,ahub-cif-ids = <6 6>;
218 status = "disable";
206 }; 219 };
207 220
208 tegra_i2s3: i2s@70080600 { 221 tegra_i2s3: i2s@70080600 {
209 compatible = "nvidia,tegra30-i2s"; 222 compatible = "nvidia,tegra30-i2s";
210 reg = <0x70080600 0x100>; 223 reg = <0x70080600 0x100>;
211 nvidia,ahub-cif-ids = <7 7>; 224 nvidia,ahub-cif-ids = <7 7>;
225 status = "disable";
212 }; 226 };
213 227
214 tegra_i2s4: i2s@70080700 { 228 tegra_i2s4: i2s@70080700 {
215 compatible = "nvidia,tegra30-i2s"; 229 compatible = "nvidia,tegra30-i2s";
216 reg = <0x70080700 0x100>; 230 reg = <0x70080700 0x100>;
217 nvidia,ahub-cif-ids = <8 8>; 231 nvidia,ahub-cif-ids = <8 8>;
232 status = "disable";
218 }; 233 };
219 }; 234 };
220 235
@@ -222,24 +237,28 @@
222 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 237 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
223 reg = <0x78000000 0x200>; 238 reg = <0x78000000 0x200>;
224 interrupts = <0 14 0x04>; 239 interrupts = <0 14 0x04>;
240 status = "disable";
225 }; 241 };
226 242
227 sdhci@78000200 { 243 sdhci@78000200 {
228 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 244 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
229 reg = <0x78000200 0x200>; 245 reg = <0x78000200 0x200>;
230 interrupts = <0 15 0x04>; 246 interrupts = <0 15 0x04>;
247 status = "disable";
231 }; 248 };
232 249
233 sdhci@78000400 { 250 sdhci@78000400 {
234 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 251 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
235 reg = <0x78000400 0x200>; 252 reg = <0x78000400 0x200>;
236 interrupts = <0 19 0x04>; 253 interrupts = <0 19 0x04>;
254 status = "disable";
237 }; 255 };
238 256
239 sdhci@78000600 { 257 sdhci@78000600 {
240 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 258 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
241 reg = <0x78000600 0x200>; 259 reg = <0x78000600 0x200>;
242 interrupts = <0 31 0x04>; 260 interrupts = <0 31 0x04>;
261 status = "disable";
243 }; 262 };
244 263
245 pmu { 264 pmu {