ARM: dt: tegra: sort nodes based on bus order

Sort the nodes according to the following rules:
* First, any overrides for properties or nodes created by included files,
  in the order they appeared in the include file.
* Second, any nodes with a reg property, in numerical order.
* Third, any nodes without a reg property, in alphabetical order of node
  name.

The second sorting rule at least will probably help if/when we need to
explicitly insert nodes for the various busses in Tegra; that will just
be an indentation change rather than also a node re-ordering.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>

1 files changed, 91 insertions, 91 deletions

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 5f9110af43b1..0e371f92d1d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,11 +4,6 @@
         compatible = "nvidia,tegra20";
         interrupt-parent = <&intc>;
 
-        pmc {
-                compatible = "nvidia,tegra20-pmc";
-                reg = <0x7000e400 0x400>;
-        };
-
         intc: interrupt-controller {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -17,12 +12,6 @@
                        0x50040100 0x0100>;
         };
 
-        pmu {
-                compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 56 0x04
-                              0 57 0x04>;
-        };
-
         apbdma: dma {
                 compatible = "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1200>;
@@ -44,55 +33,9 @@
                               0 119 0x04>;
         };
 
-        i2c@7000c000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "nvidia,tegra20-i2c";
-                reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
-        };
-
-        i2c@7000c400 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "nvidia,tegra20-i2c";
-                reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
-        };
-
-        i2c@7000c500 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "nvidia,tegra20-i2c";
-                reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
-        };
-
-        i2c@7000d000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "nvidia,tegra20-i2c-dvc";
-                reg = <0x7000d000 0x200>;
-                interrupts = <0 53 0x04>;
-        };
-
-        tegra_i2s1: i2s@70002800 {
-                compatible = "nvidia,tegra20-i2s";
-                reg = <0x70002800 0x200>;
-                interrupts = <0 13 0x04>;
-                nvidia,dma-request-selector = <&apbdma 2>;
-        };
-
-        tegra_i2s2: i2s@70002a00 {
-                compatible = "nvidia,tegra20-i2s";
-                reg = <0x70002a00 0x200>;
-                interrupts = <0 3 0x04>;
-                nvidia,dma-request-selector = <&apbdma 1>;
-        };
-
-        das {
-                compatible = "nvidia,tegra20-das";
-                reg = <0x70000c00 0x80>;
+        ahb {
+                compatible = "nvidia,tegra20-ahb";
+                reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
         };
 
         gpio: gpio {
@@ -119,6 +62,25 @@
                        0x70000868 0xa8>; /* Pad control registers */
         };
 
+        das {
+                compatible = "nvidia,tegra20-das";
+                reg = <0x70000c00 0x80>;
+        };
+
+        tegra_i2s1: i2s@70002800 {
+                compatible = "nvidia,tegra20-i2s";
+                reg = <0x70002800 0x200>;
+                interrupts = <0 13 0x04>;
+                nvidia,dma-request-selector = <&apbdma 2>;
+        };
+
+        tegra_i2s2: i2s@70002a00 {
+                compatible = "nvidia,tegra20-i2s";
+                reg = <0x70002a00 0x200>;
+                interrupts = <0 3 0x04>;
+                nvidia,dma-request-selector = <&apbdma 1>;
+        };
+
         serial@70006000 {
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
@@ -154,35 +116,61 @@
                 interrupts = <0 91 0x04>;
         };
 
-        emc {
+        i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                compatible = "nvidia,tegra20-emc";
-                reg = <0x7000f400 0x200>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000c000 0x100>;
+                interrupts = <0 38 0x04>;
         };
 
-        sdhci@c8000000 {
-                compatible = "nvidia,tegra20-sdhci";
-                reg = <0xc8000000 0x200>;
-                interrupts = <0 14 0x04>;
+        i2c@7000c400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000c400 0x100>;
+                interrupts = <0 84 0x04>;
         };
 
-        sdhci@c8000200 {
-                compatible = "nvidia,tegra20-sdhci";
-                reg = <0xc8000200 0x200>;
-                interrupts = <0 15 0x04>;
+        i2c@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c";
+                reg = <0x7000c500 0x100>;
+                interrupts = <0 92 0x04>;
         };
 
-        sdhci@c8000400 {
-                compatible = "nvidia,tegra20-sdhci";
-                reg = <0xc8000400 0x200>;
-                interrupts = <0 19 0x04>;
+        i2c@7000d000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-i2c-dvc";
+                reg = <0x7000d000 0x200>;
+                interrupts = <0 53 0x04>;
         };
 
-        sdhci@c8000600 {
-                compatible = "nvidia,tegra20-sdhci";
-                reg = <0xc8000600 0x200>;
-                interrupts = <0 31 0x04>;
+        pmc {
+                compatible = "nvidia,tegra20-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
+        mc {
+                compatible = "nvidia,tegra20-mc";
+                reg = <0x7000f000 0x024
+                       0x7000f03c 0x3c4>;
+                interrupts = <0 77 0x04>;
+        };
+
+        gart {
+                compatible = "nvidia,tegra20-gart";
+                reg = <0x7000f024 0x00000018    /* controller registers */
+                       0x58000000 0x02000000>;  /* GART aperture */
+        };
+
+        emc {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-emc";
+                reg = <0x7000f400 0x200>;
         };
 
         usb@c5000000 {
@@ -207,21 +195,33 @@
                 phy_type = "utmi";
         };
 
-        ahb {
-                compatible = "nvidia,tegra20-ahb";
-                reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
+        sdhci@c8000000 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000000 0x200>;
+                interrupts = <0 14 0x04>;
         };
 
-        mc {
-                compatible = "nvidia,tegra20-mc";
-                reg = <0x7000f000 0x024
-                       0x7000f03c 0x3c4>;
-                interrupts = <0 77 0x04>;
+        sdhci@c8000200 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000200 0x200>;
+                interrupts = <0 15 0x04>;
         };
 
-        gart {
-                compatible = "nvidia,tegra20-gart";
-                reg = <0x7000f024 0x00000018    /* controller registers */
-                       0x58000000 0x02000000>;  /* GART aperture */
+        sdhci@c8000400 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000400 0x200>;
+                interrupts = <0 19 0x04>;
+        };
+
+        sdhci@c8000600 {
+                compatible = "nvidia,tegra20-sdhci";
+                reg = <0xc8000600 0x200>;
+                interrupts = <0 31 0x04>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 56 0x04
+                              0 57 0x04>;
         };
 };