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authorStephen Warren <swarren@nvidia.com>2012-05-11 18:17:47 -0400
committerStephen Warren <swarren@nvidia.com>2012-05-14 12:55:00 -0400
commitf9eb26a4e11c63bba2fb71b58dff5ed6f33091f9 (patch)
treeddaad1df61892825401bf550871127e9c8dfe4d6 /arch/arm/boot/dts/tegra20.dtsi
parent95decf84742d712a5875bb655cd7440f6d7c1184 (diff)
ARM: dt: tegra: remove unnecessary unit addresses
DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index f98be33da708..a6b135164ae0 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,12 +4,12 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 pmc {
8 compatible = "nvidia,tegra20-pmc"; 8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>; 9 reg = <0x7000e400 0x400>;
10 }; 10 };
11 11
12 intc: interrupt-controller@50041000 { 12 intc: interrupt-controller {
13 compatible = "arm,cortex-a9-gic"; 13 compatible = "arm,cortex-a9-gic";
14 interrupt-controller; 14 interrupt-controller;
15 #interrupt-cells = <3>; 15 #interrupt-cells = <3>;
@@ -23,7 +23,7 @@
23 0 57 0x04>; 23 0 57 0x04>;
24 }; 24 };
25 25
26 apbdma: dma@6000a000 { 26 apbdma: dma {
27 compatible = "nvidia,tegra20-apbdma"; 27 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>; 28 reg = <0x6000a000 0x1200>;
29 interrupts = <0 104 0x04 29 interrupts = <0 104 0x04
@@ -90,12 +90,12 @@
90 nvidia,dma-request-selector = <&apbdma 1>; 90 nvidia,dma-request-selector = <&apbdma 1>;
91 }; 91 };
92 92
93 das@70000c00 { 93 das {
94 compatible = "nvidia,tegra20-das"; 94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>; 95 reg = <0x70000c00 0x80>;
96 }; 96 };
97 97
98 gpio: gpio@6000d000 { 98 gpio: gpio {
99 compatible = "nvidia,tegra20-gpio"; 99 compatible = "nvidia,tegra20-gpio";
100 reg = <0x6000d000 0x1000>; 100 reg = <0x6000d000 0x1000>;
101 interrupts = <0 32 0x04 101 interrupts = <0 32 0x04
@@ -111,7 +111,7 @@
111 interrupt-controller; 111 interrupt-controller;
112 }; 112 };
113 113
114 pinmux: pinmux@70000000 { 114 pinmux: pinmux {
115 compatible = "nvidia,tegra20-pinmux"; 115 compatible = "nvidia,tegra20-pinmux";
116 reg = <0x70000014 0x10 /* Tri-state registers */ 116 reg = <0x70000014 0x10 /* Tri-state registers */
117 0x70000080 0x20 /* Mux registers */ 117 0x70000080 0x20 /* Mux registers */
@@ -154,7 +154,7 @@
154 interrupts = <0 91 0x04>; 154 interrupts = <0 91 0x04>;
155 }; 155 };
156 156
157 emc@7000f400 { 157 emc {
158 #address-cells = <1>; 158 #address-cells = <1>;
159 #size-cells = <0>; 159 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc"; 160 compatible = "nvidia,tegra20-emc";
@@ -207,7 +207,7 @@
207 phy_type = "utmi"; 207 phy_type = "utmi";
208 }; 208 };
209 209
210 ahb: ahb@6000c004 { 210 ahb {
211 compatible = "nvidia,tegra20-ahb"; 211 compatible = "nvidia,tegra20-ahb";
212 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 212 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
213 }; 213 };