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authorpdeschrijver@nvidia.com <pdeschrijver@nvidia.com>2011-11-29 20:29:19 -0500
committerOlof Johansson <olof@lixom.net>2011-12-08 00:20:12 -0500
commit0d4f74792e2946cb2ef40a1673851eda1041358c (patch)
tree3a09fab581dff11adf0df12ce84c77bea15a164b /arch/arm/boot/dts/tegra20.dtsi
parent1292c129597ce42a75d9e97cd312c3242e10a6f3 (diff)
arm/tegra: convert tegra20 to GIC devicetree binding
Convert tegra20 IRQ intialization to the GIC devicetree binding. Modify the interrupt definitions in the dts files according to Documentation/devicetree/bindings/arm/gic.txt v3 (swarren): * Moved of_irq_init() call into board-dt.c to avoid ifdef'ing it. - Even with a dummy replacement if !CONFIG_OF, the reference from tegra_dt_irq_match[] to gic_of_init() would still have to be ifdef'd - It's plausible that tegra_dt_irq_match[] may need to contain more entries in the future, and defining what they are seems more suitable for board-dt.c than irq.c v2 (swarren): * Removed some stale GIC init code from board-dt.c * Undid some accidental 0x -> 0x0 search/replace. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> [olof: added include of <asm/hardware/gic.h> for compile to pass] Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi48
1 files changed, 27 insertions, 21 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 04068dd49286..660c8ad537c0 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -5,9 +5,9 @@
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 intc: interrupt-controller@50041000 { 7 intc: interrupt-controller@50041000 {
8 compatible = "nvidia,tegra20-gic"; 8 compatible = "arm,cortex-a9-gic";
9 interrupt-controller; 9 interrupt-controller;
10 #interrupt-cells = <1>; 10 #interrupt-cells = <3>;
11 reg = < 0x50041000 0x1000 >, 11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >; 12 < 0x50040100 0x0100 >;
13 }; 13 };
@@ -17,7 +17,7 @@
17 #size-cells = <0>; 17 #size-cells = <0>;
18 compatible = "nvidia,tegra20-i2c"; 18 compatible = "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>; 19 reg = <0x7000C000 0x100>;
20 interrupts = < 70 >; 20 interrupts = < 0 38 0x04 >;
21 }; 21 };
22 22
23 i2c@7000c400 { 23 i2c@7000c400 {
@@ -25,7 +25,7 @@
25 #size-cells = <0>; 25 #size-cells = <0>;
26 compatible = "nvidia,tegra20-i2c"; 26 compatible = "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>; 27 reg = <0x7000C400 0x100>;
28 interrupts = < 116 >; 28 interrupts = < 0 84 0x04 >;
29 }; 29 };
30 30
31 i2c@7000c500 { 31 i2c@7000c500 {
@@ -33,7 +33,7 @@
33 #size-cells = <0>; 33 #size-cells = <0>;
34 compatible = "nvidia,tegra20-i2c"; 34 compatible = "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>; 35 reg = <0x7000C500 0x100>;
36 interrupts = < 124 >; 36 interrupts = < 0 92 0x04 >;
37 }; 37 };
38 38
39 i2c@7000d000 { 39 i2c@7000d000 {
@@ -41,20 +41,20 @@
41 #size-cells = <0>; 41 #size-cells = <0>;
42 compatible = "nvidia,tegra20-i2c"; 42 compatible = "nvidia,tegra20-i2c";
43 reg = <0x7000D000 0x200>; 43 reg = <0x7000D000 0x200>;
44 interrupts = < 85 >; 44 interrupts = < 0 53 0x04 >;
45 }; 45 };
46 46
47 i2s@70002800 { 47 i2s@70002800 {
48 compatible = "nvidia,tegra20-i2s"; 48 compatible = "nvidia,tegra20-i2s";
49 reg = <0x70002800 0x200>; 49 reg = <0x70002800 0x200>;
50 interrupts = < 45 >; 50 interrupts = < 0 13 0x04 >;
51 dma-channel = < 2 >; 51 dma-channel = < 2 >;
52 }; 52 };
53 53
54 i2s@70002a00 { 54 i2s@70002a00 {
55 compatible = "nvidia,tegra20-i2s"; 55 compatible = "nvidia,tegra20-i2s";
56 reg = <0x70002a00 0x200>; 56 reg = <0x70002a00 0x200>;
57 interrupts = < 35 >; 57 interrupts = < 0 3 0x04 >;
58 dma-channel = < 1 >; 58 dma-channel = < 1 >;
59 }; 59 };
60 60
@@ -66,7 +66,13 @@
66 gpio: gpio@6000d000 { 66 gpio: gpio@6000d000 {
67 compatible = "nvidia,tegra20-gpio"; 67 compatible = "nvidia,tegra20-gpio";
68 reg = < 0x6000d000 0x1000 >; 68 reg = < 0x6000d000 0x1000 >;
69 interrupts = < 64 65 66 67 87 119 121 >; 69 interrupts = < 0 32 0x04
70 0 33 0x04
71 0 34 0x04
72 0 35 0x04
73 0 55 0x04
74 0 87 0x04
75 0 89 0x04 >;
70 #gpio-cells = <2>; 76 #gpio-cells = <2>;
71 gpio-controller; 77 gpio-controller;
72 }; 78 };
@@ -83,79 +89,79 @@
83 compatible = "nvidia,tegra20-uart"; 89 compatible = "nvidia,tegra20-uart";
84 reg = <0x70006000 0x40>; 90 reg = <0x70006000 0x40>;
85 reg-shift = <2>; 91 reg-shift = <2>;
86 interrupts = < 68 >; 92 interrupts = < 0 36 0x04 >;
87 }; 93 };
88 94
89 serial@70006040 { 95 serial@70006040 {
90 compatible = "nvidia,tegra20-uart"; 96 compatible = "nvidia,tegra20-uart";
91 reg = <0x70006040 0x40>; 97 reg = <0x70006040 0x40>;
92 reg-shift = <2>; 98 reg-shift = <2>;
93 interrupts = < 69 >; 99 interrupts = < 0 37 0x04 >;
94 }; 100 };
95 101
96 serial@70006200 { 102 serial@70006200 {
97 compatible = "nvidia,tegra20-uart"; 103 compatible = "nvidia,tegra20-uart";
98 reg = <0x70006200 0x100>; 104 reg = <0x70006200 0x100>;
99 reg-shift = <2>; 105 reg-shift = <2>;
100 interrupts = < 78 >; 106 interrupts = < 0 46 0x04 >;
101 }; 107 };
102 108
103 serial@70006300 { 109 serial@70006300 {
104 compatible = "nvidia,tegra20-uart"; 110 compatible = "nvidia,tegra20-uart";
105 reg = <0x70006300 0x100>; 111 reg = <0x70006300 0x100>;
106 reg-shift = <2>; 112 reg-shift = <2>;
107 interrupts = < 122 >; 113 interrupts = < 0 90 0x04 >;
108 }; 114 };
109 115
110 serial@70006400 { 116 serial@70006400 {
111 compatible = "nvidia,tegra20-uart"; 117 compatible = "nvidia,tegra20-uart";
112 reg = <0x70006400 0x100>; 118 reg = <0x70006400 0x100>;
113 reg-shift = <2>; 119 reg-shift = <2>;
114 interrupts = < 123 >; 120 interrupts = < 0 91 0x04 >;
115 }; 121 };
116 122
117 sdhci@c8000000 { 123 sdhci@c8000000 {
118 compatible = "nvidia,tegra20-sdhci"; 124 compatible = "nvidia,tegra20-sdhci";
119 reg = <0xc8000000 0x200>; 125 reg = <0xc8000000 0x200>;
120 interrupts = < 46 >; 126 interrupts = < 0 14 0x04 >;
121 }; 127 };
122 128
123 sdhci@c8000200 { 129 sdhci@c8000200 {
124 compatible = "nvidia,tegra20-sdhci"; 130 compatible = "nvidia,tegra20-sdhci";
125 reg = <0xc8000200 0x200>; 131 reg = <0xc8000200 0x200>;
126 interrupts = < 47 >; 132 interrupts = < 0 15 0x04 >;
127 }; 133 };
128 134
129 sdhci@c8000400 { 135 sdhci@c8000400 {
130 compatible = "nvidia,tegra20-sdhci"; 136 compatible = "nvidia,tegra20-sdhci";
131 reg = <0xc8000400 0x200>; 137 reg = <0xc8000400 0x200>;
132 interrupts = < 51 >; 138 interrupts = < 0 19 0x04 >;
133 }; 139 };
134 140
135 sdhci@c8000600 { 141 sdhci@c8000600 {
136 compatible = "nvidia,tegra20-sdhci"; 142 compatible = "nvidia,tegra20-sdhci";
137 reg = <0xc8000600 0x200>; 143 reg = <0xc8000600 0x200>;
138 interrupts = < 63 >; 144 interrupts = < 0 31 0x04 >;
139 }; 145 };
140 146
141 usb@c5000000 { 147 usb@c5000000 {
142 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 148 compatible = "nvidia,tegra20-ehci", "usb-ehci";
143 reg = <0xc5000000 0x4000>; 149 reg = <0xc5000000 0x4000>;
144 interrupts = < 52 >; 150 interrupts = < 0 20 0x04 >;
145 phy_type = "utmi"; 151 phy_type = "utmi";
146 }; 152 };
147 153
148 usb@c5004000 { 154 usb@c5004000 {
149 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 155 compatible = "nvidia,tegra20-ehci", "usb-ehci";
150 reg = <0xc5004000 0x4000>; 156 reg = <0xc5004000 0x4000>;
151 interrupts = < 53 >; 157 interrupts = < 0 21 0x04 >;
152 phy_type = "ulpi"; 158 phy_type = "ulpi";
153 }; 159 };
154 160
155 usb@c5008000 { 161 usb@c5008000 {
156 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 162 compatible = "nvidia,tegra20-ehci", "usb-ehci";
157 reg = <0xc5008000 0x4000>; 163 reg = <0xc5008000 0x4000>;
158 interrupts = < 129 >; 164 interrupts = < 0 97 0x04 >;
159 phy_type = "utmi"; 165 phy_type = "utmi";
160 }; 166 };
161}; 167};