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authorStephen Warren <swarren@nvidia.com>2012-04-20 18:57:38 -0400
committerStephen Warren <swarren@nvidia.com>2012-07-06 14:27:35 -0400
commitc80efbae6a53d9702630fc5f96662f96a45ca56a (patch)
tree2cceecca06cc3865c86921134dc2f1341155e660 /arch/arm/boot/dts/tegra20-whistler.dts
parent702b0e4f2f2782962aab7d9a0a40ad68770bb1f6 (diff)
ARM: dt: tegra: add Whistler device tree file
Whistler is a highly configurable Tegra evaluation and development board. This change adds support for the following specific configuration: E1120 motherboard E1108 CPU board E1116 PMU board The motherboard configuration switches are set as follows: SW1=0 SW2=0 SW3=5 S1/S2/S3/S4 all on, except S3 7/8 are off. Other combinations of daugher boards may work to varying degrees, but will likely require some SW adjustment. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-whistler.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts301
1 files changed, 301 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
new file mode 100644
index 000000000000..6916310bf58f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -0,0 +1,301 @@
1/dts-v1/;
2
3/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Whistler evaluation board";
7 compatible = "nvidia,whistler", "nvidia,tegra20";
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 pinmux {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
20 "gmc", "gmd", "gpu";
21 nvidia,function = "gmi";
22 };
23 atc {
24 nvidia,pins = "atc", "atd";
25 nvidia,function = "sdio4";
26 };
27 cdev1 {
28 nvidia,pins = "cdev1";
29 nvidia,function = "plla_out";
30 };
31 cdev2 {
32 nvidia,pins = "cdev2";
33 nvidia,function = "osc";
34 };
35 crtp {
36 nvidia,pins = "crtp";
37 nvidia,function = "crt";
38 };
39 csus {
40 nvidia,pins = "csus";
41 nvidia,function = "vi_sensor_clk";
42 };
43 dap1 {
44 nvidia,pins = "dap1";
45 nvidia,function = "dap1";
46 };
47 dap2 {
48 nvidia,pins = "dap2";
49 nvidia,function = "dap2";
50 };
51 dap3 {
52 nvidia,pins = "dap3";
53 nvidia,function = "dap3";
54 };
55 dap4 {
56 nvidia,pins = "dap4";
57 nvidia,function = "dap4";
58 };
59 ddc {
60 nvidia,pins = "ddc";
61 nvidia,function = "i2c2";
62 };
63 dta {
64 nvidia,pins = "dta", "dtb", "dtc", "dtd";
65 nvidia,function = "vi";
66 };
67 dte {
68 nvidia,pins = "dte";
69 nvidia,function = "rsvd1";
70 };
71 dtf {
72 nvidia,pins = "dtf";
73 nvidia,function = "i2c3";
74 };
75 gme {
76 nvidia,pins = "gme";
77 nvidia,function = "dap5";
78 };
79 gpu7 {
80 nvidia,pins = "gpu7";
81 nvidia,function = "rtck";
82 };
83 gpv {
84 nvidia,pins = "gpv";
85 nvidia,function = "pcie";
86 };
87 hdint {
88 nvidia,pins = "hdint", "pta";
89 nvidia,function = "hdmi";
90 };
91 i2cp {
92 nvidia,pins = "i2cp";
93 nvidia,function = "i2cp";
94 };
95 irrx {
96 nvidia,pins = "irrx", "irtx";
97 nvidia,function = "uartb";
98 };
99 kbca {
100 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
101 nvidia,function = "kbc";
102 };
103 kbcb {
104 nvidia,pins = "kbcb", "kbcd";
105 nvidia,function = "sdio2";
106 };
107 lcsn {
108 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
109 "spia", "spib", "spic";
110 nvidia,function = "spi3";
111 };
112 ld0 {
113 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
114 "ld5", "ld6", "ld7", "ld8", "ld9",
115 "ld10", "ld11", "ld12", "ld13", "ld14",
116 "ld15", "ld16", "ld17", "ldc", "ldi",
117 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
118 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
119 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "owr";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
137 "slxc", "slxd", "slxk";
138 nvidia,function = "sdio3";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 spdi {
145 nvidia,pins = "spdi", "spdo";
146 nvidia,function = "rsvd2";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spig", "spih";
150 nvidia,function = "spi2_alt";
151 };
152 spif {
153 nvidia,pins = "spif";
154 nvidia,function = "spi2";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab";
158 nvidia,function = "uarta";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 uda {
169 nvidia,pins = "uda";
170 nvidia,function = "spi1";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
174 "gmb", "gmc", "gmd", "irrx", "irtx",
175 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
176 "kbcf", "sdc", "sdd", "spie", "spig",
177 "spih", "uaa", "uab", "uad", "uca",
178 "ucb";
179 nvidia,pull = <2>;
180 nvidia,tristate = <0>;
181 };
182 conf_atd {
183 nvidia,pins = "atd", "ate", "cdev1", "csus",
184 "dap1", "dap2", "dap3", "dap4", "dte",
185 "dtf", "gpu", "gpu7", "gpv", "i2cp",
186 "rm", "sdio1", "slxa", "slxc", "slxd",
187 "slxk", "spdi", "spdo", "uac", "uda";
188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
191 conf_cdev2 {
192 nvidia,pins = "cdev2", "spia", "spib";
193 nvidia,pull = <1>;
194 nvidia,tristate = <1>;
195 };
196 conf_ck32 {
197 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
198 "pmcb", "pmcc", "pmcd", "xm2c",
199 "xm2d";
200 nvidia,pull = <0>;
201 };
202 conf_crtp {
203 nvidia,pins = "crtp";
204 nvidia,pull = <0>;
205 nvidia,tristate = <1>;
206 };
207 conf_dta {
208 nvidia,pins = "dta", "dtb", "dtc", "dtd",
209 "spid", "spif";
210 nvidia,pull = <1>;
211 nvidia,tristate = <0>;
212 };
213 conf_gme {
214 nvidia,pins = "gme", "owc", "pta", "spic";
215 nvidia,pull = <2>;
216 nvidia,tristate = <1>;
217 };
218 conf_ld17_0 {
219 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
220 "ld23_22";
221 nvidia,pull = <1>;
222 };
223 conf_ls {
224 nvidia,pins = "ls", "pmce";
225 nvidia,pull = <2>;
226 };
227 drive_dap1 {
228 nvidia,pins = "drive_dap1";
229 nvidia,high-speed-mode = <0>;
230 nvidia,schmitt = <1>;
231 nvidia,low-power-mode = <0>;
232 nvidia,pull-down-strength = <0>;
233 nvidia,pull-up-strength = <0>;
234 nvidia,slew-rate-rising = <0>;
235 nvidia,slew-rate-falling = <0>;
236 };
237 };
238 };
239
240 i2s@70002800 {
241 status = "okay";
242 };
243
244 serial@70006000 {
245 status = "okay";
246 clock-frequency = <216000000>;
247 };
248
249 i2c@7000d000 {
250 status = "okay";
251 clock-frequency = <100000>;
252
253 codec: codec@1a {
254 compatible = "wlf,wm8753";
255 reg = <0x1a>;
256 };
257
258 tca6416: gpio@20 {
259 compatible = "ti,tca6416";
260 reg = <0x20>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 };
264 };
265
266 usb@c5000000 {
267 status = "okay";
268 nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
269 };
270
271 usb@c5008000 {
272 status = "okay";
273 nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
274 };
275
276 sdhci@c8000400 {
277 status = "okay";
278 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
279 bus-width = <8>;
280 };
281
282 sdhci@c8000600 {
283 status = "okay";
284 bus-width = <8>;
285 };
286
287 sound {
288 compatible = "nvidia,tegra-audio-wm8753-whistler",
289 "nvidia,tegra-audio-wm8753";
290 nvidia,model = "NVIDIA Tegra Whistler";
291
292 nvidia,audio-routing =
293 "Headphone Jack", "LOUT1",
294 "Headphone Jack", "ROUT1",
295 "MIC2", "Mic Jack",
296 "MIC2N", "Mic Jack";
297
298 nvidia,i2s-controller = <&tegra_i2s1>;
299 nvidia,audio-codec = <&codec>;
300 };
301};