diff options
author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-12-05 05:44:08 -0500 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 16:09:20 -0500 |
commit | ba4104e79470ae848a9f38029fe1371790dc0df9 (patch) | |
tree | dce17889fa0d113096a0648325420e10b5c38bc8 /arch/arm/boot/dts/tegra20-whistler.dts | |
parent | 5fc6b0dd319c5b726b4cad379bea6ddd3b4a380f (diff) |
ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-whistler.dts')
-rw-r--r-- | arch/arm/boot/dts/tegra20-whistler.dts | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 00ba97a916f8..813b04ef8717 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
@@ -190,8 +190,8 @@ | |||
190 | "kbcf", "sdc", "sdd", "spie", "spig", | 190 | "kbcf", "sdc", "sdd", "spie", "spig", |
191 | "spih", "uaa", "uab", "uad", "uca", | 191 | "spih", "uaa", "uab", "uad", "uca", |
192 | "ucb"; | 192 | "ucb"; |
193 | nvidia,pull = <2>; | 193 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
194 | nvidia,tristate = <0>; | 194 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
195 | }; | 195 | }; |
196 | conf_atd { | 196 | conf_atd { |
197 | nvidia,pins = "atd", "ate", "cdev1", "csus", | 197 | nvidia,pins = "atd", "ate", "cdev1", "csus", |
@@ -199,54 +199,54 @@ | |||
199 | "dtf", "gpu", "gpu7", "gpv", "i2cp", | 199 | "dtf", "gpu", "gpu7", "gpv", "i2cp", |
200 | "rm", "sdio1", "slxa", "slxc", "slxd", | 200 | "rm", "sdio1", "slxa", "slxc", "slxd", |
201 | "slxk", "spdi", "spdo", "uac", "uda"; | 201 | "slxk", "spdi", "spdo", "uac", "uda"; |
202 | nvidia,pull = <0>; | 202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
203 | nvidia,tristate = <0>; | 203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
204 | }; | 204 | }; |
205 | conf_cdev2 { | 205 | conf_cdev2 { |
206 | nvidia,pins = "cdev2", "spia", "spib"; | 206 | nvidia,pins = "cdev2", "spia", "spib"; |
207 | nvidia,pull = <1>; | 207 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
208 | nvidia,tristate = <1>; | 208 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
209 | }; | 209 | }; |
210 | conf_ck32 { | 210 | conf_ck32 { |
211 | nvidia,pins = "ck32", "ddrc", "lc", "pmca", | 211 | nvidia,pins = "ck32", "ddrc", "lc", "pmca", |
212 | "pmcb", "pmcc", "pmcd", "xm2c", | 212 | "pmcb", "pmcc", "pmcd", "xm2c", |
213 | "xm2d"; | 213 | "xm2d"; |
214 | nvidia,pull = <0>; | 214 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
215 | }; | 215 | }; |
216 | conf_crtp { | 216 | conf_crtp { |
217 | nvidia,pins = "crtp"; | 217 | nvidia,pins = "crtp"; |
218 | nvidia,pull = <0>; | 218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
219 | nvidia,tristate = <1>; | 219 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
220 | }; | 220 | }; |
221 | conf_dta { | 221 | conf_dta { |
222 | nvidia,pins = "dta", "dtb", "dtc", "dtd", | 222 | nvidia,pins = "dta", "dtb", "dtc", "dtd", |
223 | "spid", "spif"; | 223 | "spid", "spif"; |
224 | nvidia,pull = <1>; | 224 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
225 | nvidia,tristate = <0>; | 225 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
226 | }; | 226 | }; |
227 | conf_gme { | 227 | conf_gme { |
228 | nvidia,pins = "gme", "owc", "pta", "spic"; | 228 | nvidia,pins = "gme", "owc", "pta", "spic"; |
229 | nvidia,pull = <2>; | 229 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
230 | nvidia,tristate = <1>; | 230 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
231 | }; | 231 | }; |
232 | conf_ld17_0 { | 232 | conf_ld17_0 { |
233 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | 233 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
234 | "ld23_22"; | 234 | "ld23_22"; |
235 | nvidia,pull = <1>; | 235 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
236 | }; | 236 | }; |
237 | conf_ls { | 237 | conf_ls { |
238 | nvidia,pins = "ls", "pmce"; | 238 | nvidia,pins = "ls", "pmce"; |
239 | nvidia,pull = <2>; | 239 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
240 | }; | 240 | }; |
241 | drive_dap1 { | 241 | drive_dap1 { |
242 | nvidia,pins = "drive_dap1"; | 242 | nvidia,pins = "drive_dap1"; |
243 | nvidia,high-speed-mode = <0>; | 243 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
244 | nvidia,schmitt = <1>; | 244 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
245 | nvidia,low-power-mode = <0>; | 245 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>; |
246 | nvidia,pull-down-strength = <0>; | 246 | nvidia,pull-down-strength = <0>; |
247 | nvidia,pull-up-strength = <0>; | 247 | nvidia,pull-up-strength = <0>; |
248 | nvidia,slew-rate-rising = <0>; | 248 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
249 | nvidia,slew-rate-falling = <0>; | 249 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
250 | }; | 250 | }; |
251 | }; | 251 | }; |
252 | }; | 252 | }; |