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authorLucas Stach <dev@lynxeye.de>2013-01-22 16:46:07 -0500
committerStephen Warren <swarren@nvidia.com>2013-01-28 13:24:09 -0500
commitab343e91aa00d6cc1047e8209d610c384ee824b9 (patch)
treed8e4ba8a829d4c1b6922ac511de9df27521ccb22 /arch/arm/boot/dts/tegra20-whistler.dts
parentc0967ce0a7388fa8818f5529897140f4f7ec8543 (diff)
ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-whistler.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index b8e0ee1d2172..ea57c0f6dcce 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -255,7 +255,6 @@
255 255
256 serial@70006000 { 256 serial@70006000 {
257 status = "okay"; 257 status = "okay";
258 clock-frequency = <216000000>;
259 }; 258 };
260 259
261 hdmi_ddc: i2c@7000c400 { 260 hdmi_ddc: i2c@7000c400 {