diff options
author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-12-05 05:44:08 -0500 |
---|---|---|
committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 16:09:20 -0500 |
commit | ba4104e79470ae848a9f38029fe1371790dc0df9 (patch) | |
tree | dce17889fa0d113096a0648325420e10b5c38bc8 /arch/arm/boot/dts/tegra20-trimslice.dts | |
parent | 5fc6b0dd319c5b726b4cad379bea6ddd3b4a380f (diff) |
ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
-rw-r--r-- | arch/arm/boot/dts/tegra20-trimslice.dts | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index babc8fbf1663..ec36fafb0f90 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
@@ -192,49 +192,49 @@ | |||
192 | "dtb", "dtc", "dtd", "dte", "gmb", | 192 | "dtb", "dtc", "dtd", "dte", "gmb", |
193 | "gme", "i2cp", "pta", "slxc", "slxd", | 193 | "gme", "i2cp", "pta", "slxc", "slxd", |
194 | "spdi", "spdo", "uda"; | 194 | "spdi", "spdo", "uda"; |
195 | nvidia,pull = <0>; | 195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
196 | nvidia,tristate = <1>; | 196 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
197 | }; | 197 | }; |
198 | conf_atb { | 198 | conf_atb { |
199 | nvidia,pins = "atb", "cdev1", "cdev2", "dap1", | 199 | nvidia,pins = "atb", "cdev1", "cdev2", "dap1", |
200 | "gma", "gmc", "gmd", "gpu", "gpu7", | 200 | "gma", "gmc", "gmd", "gpu", "gpu7", |
201 | "gpv", "sdio1", "slxa", "slxk", "uac"; | 201 | "gpv", "sdio1", "slxa", "slxk", "uac"; |
202 | nvidia,pull = <0>; | 202 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
203 | nvidia,tristate = <0>; | 203 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
204 | }; | 204 | }; |
205 | conf_ck32 { | 205 | conf_ck32 { |
206 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | 206 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
207 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | 207 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
208 | nvidia,pull = <0>; | 208 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
209 | }; | 209 | }; |
210 | conf_csus { | 210 | conf_csus { |
211 | nvidia,pins = "csus", "spia", "spib", | 211 | nvidia,pins = "csus", "spia", "spib", |
212 | "spid", "spif"; | 212 | "spid", "spif"; |
213 | nvidia,pull = <1>; | 213 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
214 | nvidia,tristate = <1>; | 214 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
215 | }; | 215 | }; |
216 | conf_ddc { | 216 | conf_ddc { |
217 | nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; | 217 | nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; |
218 | nvidia,pull = <2>; | 218 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
219 | nvidia,tristate = <0>; | 219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
220 | }; | 220 | }; |
221 | conf_hdint { | 221 | conf_hdint { |
222 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | 222 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
223 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | 223 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
224 | "lvp0", "pmc"; | 224 | "lvp0", "pmc"; |
225 | nvidia,tristate = <1>; | 225 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
226 | }; | 226 | }; |
227 | conf_irrx { | 227 | conf_irrx { |
228 | nvidia,pins = "irrx", "irtx", "kbca", "kbcb", | 228 | nvidia,pins = "irrx", "irtx", "kbca", "kbcb", |
229 | "kbcc", "kbcd", "kbce", "kbcf", "owc", | 229 | "kbcc", "kbcd", "kbce", "kbcf", "owc", |
230 | "spic", "spie", "spig", "spih", "uaa", | 230 | "spic", "spie", "spig", "spih", "uaa", |
231 | "uab", "uad", "uca", "ucb"; | 231 | "uab", "uad", "uca", "ucb"; |
232 | nvidia,pull = <2>; | 232 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
233 | nvidia,tristate = <1>; | 233 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
234 | }; | 234 | }; |
235 | conf_lc { | 235 | conf_lc { |
236 | nvidia,pins = "lc", "ls"; | 236 | nvidia,pins = "lc", "ls"; |
237 | nvidia,pull = <2>; | 237 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
238 | }; | 238 | }; |
239 | conf_ld0 { | 239 | conf_ld0 { |
240 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | 240 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
@@ -244,17 +244,17 @@ | |||
244 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | 244 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
245 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | 245 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
246 | "lvs", "sdb"; | 246 | "lvs", "sdb"; |
247 | nvidia,tristate = <0>; | 247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
248 | }; | 248 | }; |
249 | conf_ld17_0 { | 249 | conf_ld17_0 { |
250 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | 250 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
251 | "ld23_22"; | 251 | "ld23_22"; |
252 | nvidia,pull = <1>; | 252 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
253 | }; | 253 | }; |
254 | conf_spif { | 254 | conf_spif { |
255 | nvidia,pins = "spif"; | 255 | nvidia,pins = "spif"; |
256 | nvidia,pull = <1>; | 256 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
257 | nvidia,tristate = <0>; | 257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
258 | }; | 258 | }; |
259 | }; | 259 | }; |
260 | }; | 260 | }; |