ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines

Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

1 files changed, 22 insertions, 22 deletions

diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 476e4e8bf7cb..1204738dbf29 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -190,53 +190,53 @@
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxd", "slxk", "spdi", "spdo", "uac",
                                         "uad", "uca", "ucb", "uda";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ate {
                                 nvidia,pins = "ate", "csus", "dap3",
                                         "gpv", "owc", "slxc", "spib", "spid",
                                         "spie";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_ck32 {
                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
-                                nvidia,pull = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                         };
                         conf_crtp {
                                 nvidia,pins = "crtp", "gmb", "slxa", "spia",
                                         "spig", "spih";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_dte {
                                 nvidia,pins = "dte", "spif";
-                                nvidia,pull = <1>;
-                                nvidia,tristate = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_hdint {
                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
                                         "lvp0";
-                                nvidia,tristate = <1>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
                         conf_kbca {
                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
                                         "kbce", "kbcf", "sdio1", "spic", "uaa",
                                         "uab";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_lc {
                                 nvidia,pins = "lc", "ls";
-                                nvidia,pull = <2>;
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                         };
                         conf_ld0 {
                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -246,22 +246,22 @@
                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
                                         "lvs", "pmc", "sdb";
-                                nvidia,tristate = <0>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         conf_ld17_0 {
                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
                                         "ld23_22";
-                                nvidia,pull = <1>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                         };
                         drive_sdio1 {
                                 nvidia,pins = "drive_sdio1";
-                                nvidia,high-speed-mode = <0>;
-                                nvidia,schmitt = <0>;
-                                nvidia,low-power-mode = <3>;
+                                nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
                                 nvidia,pull-down-strength = <31>;
                                 nvidia,pull-up-strength = <31>;
-                                nvidia,slew-rate-rising = <3>;
-                                nvidia,slew-rate-falling = <3>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
                         };
                 };