diff options
| author | Thierry Reding <thierry.reding@gmail.com> | 2013-12-13 11:24:05 -0500 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 16:09:22 -0500 |
| commit | 9f1ac5606a008f4849208ebfe818f979619dced0 (patch) | |
| tree | 16ba1eb39a7a80e10ee89f6b2cb2ec2b8526b87e /arch/arm/boot/dts/tegra124.dtsi | |
| parent | f5cb19b496300e6b4f8e4da119cc4bf959ab1baa (diff) | |
ARM: tegra: Add SPI controller nodes for Tegra124
The SPI controllers on Tegra124 are compatible with those found on the
Tegra114 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6fd4959d59b5..ec0698a8354a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi | |||
| @@ -277,6 +277,96 @@ | |||
| 277 | status = "disabled"; | 277 | status = "disabled"; |
| 278 | }; | 278 | }; |
| 279 | 279 | ||
| 280 | spi@7000d400 { | ||
| 281 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | ||
| 282 | reg = <0x7000d400 0x200>; | ||
| 283 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; | ||
| 284 | #address-cells = <1>; | ||
| 285 | #size-cells = <0>; | ||
| 286 | clocks = <&tegra_car TEGRA124_CLK_SBC1>; | ||
| 287 | clock-names = "spi"; | ||
| 288 | resets = <&tegra_car 41>; | ||
| 289 | reset-names = "spi"; | ||
| 290 | dmas = <&apbdma 15>, <&apbdma 15>; | ||
| 291 | dma-names = "rx", "tx"; | ||
| 292 | status = "disabled"; | ||
| 293 | }; | ||
| 294 | |||
| 295 | spi@7000d600 { | ||
| 296 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | ||
| 297 | reg = <0x7000d600 0x200>; | ||
| 298 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | ||
| 299 | #address-cells = <1>; | ||
| 300 | #size-cells = <0>; | ||
| 301 | clocks = <&tegra_car TEGRA124_CLK_SBC2>; | ||
| 302 | clock-names = "spi"; | ||
| 303 | resets = <&tegra_car 44>; | ||
| 304 | reset-names = "spi"; | ||
| 305 | dmas = <&apbdma 16>, <&apbdma 16>; | ||
| 306 | dma-names = "rx", "tx"; | ||
| 307 | status = "disabled"; | ||
| 308 | }; | ||
| 309 | |||
| 310 | spi@7000d800 { | ||
| 311 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | ||
| 312 | reg = <0x7000d800 0x200>; | ||
| 313 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | ||
| 314 | #address-cells = <1>; | ||
| 315 | #size-cells = <0>; | ||
| 316 | clocks = <&tegra_car TEGRA124_CLK_SBC3>; | ||
| 317 | clock-names = "spi"; | ||
| 318 | resets = <&tegra_car 46>; | ||
| 319 | reset-names = "spi"; | ||
| 320 | dmas = <&apbdma 17>, <&apbdma 17>; | ||
| 321 | dma-names = "rx", "tx"; | ||
| 322 | status = "disabled"; | ||
| 323 | }; | ||
| 324 | |||
| 325 | spi@7000da00 { | ||
| 326 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | ||
| 327 | reg = <0x7000da00 0x200>; | ||
| 328 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | ||
| 329 | #address-cells = <1>; | ||
| 330 | #size-cells = <0>; | ||
| 331 | clocks = <&tegra_car TEGRA124_CLK_SBC4>; | ||
| 332 | clock-names = "spi"; | ||
| 333 | resets = <&tegra_car 68>; | ||
| 334 | reset-names = "spi"; | ||
| 335 | dmas = <&apbdma 18>, <&apbdma 18>; | ||
| 336 | dma-names = "rx", "tx"; | ||
| 337 | status = "disabled"; | ||
| 338 | }; | ||
| 339 | |||
| 340 | spi@7000dc00 { | ||
| 341 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | ||
| 342 | reg = <0x7000dc00 0x200>; | ||
| 343 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | ||
| 344 | #address-cells = <1>; | ||
| 345 | #size-cells = <0>; | ||
| 346 | clocks = <&tegra_car TEGRA124_CLK_SBC5>; | ||
| 347 | clock-names = "spi"; | ||
| 348 | resets = <&tegra_car 104>; | ||
| 349 | reset-names = "spi"; | ||
| 350 | dmas = <&apbdma 27>, <&apbdma 27>; | ||
| 351 | dma-names = "rx", "tx"; | ||
| 352 | status = "disabled"; | ||
| 353 | }; | ||
| 354 | |||
| 355 | spi@7000de00 { | ||
| 356 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; | ||
| 357 | reg = <0x7000de00 0x200>; | ||
| 358 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | ||
| 359 | #address-cells = <1>; | ||
| 360 | #size-cells = <0>; | ||
| 361 | clocks = <&tegra_car TEGRA124_CLK_SBC6>; | ||
| 362 | clock-names = "spi"; | ||
| 363 | resets = <&tegra_car 105>; | ||
| 364 | reset-names = "spi"; | ||
| 365 | dmas = <&apbdma 28>, <&apbdma 28>; | ||
| 366 | dma-names = "rx", "tx"; | ||
| 367 | status = "disabled"; | ||
| 368 | }; | ||
| 369 | |||
| 280 | rtc@7000e000 { | 370 | rtc@7000e000 { |
| 281 | compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; | 371 | compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; |
| 282 | reg = <0x7000e000 0x100>; | 372 | reg = <0x7000e000 0x100>; |