Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes contain the usual driver additions,
  enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
  devices.

  Additionally the framework core underwent a bit of surgery with two
  major changes:

   - The boundary between the clock core and clock providers (e.g clock
     drivers) is now more well defined with dedicated provider helper
     functions.  struct clk no longer maps 1:1 with the hardware clock
     but is a true per-user cookie which helps us tracker users of
     hardware clocks and debug bad behavior.

   - The addition of rate constraints for clocks.  Rate ranges are now
     supported which are analogous to the voltage ranges in the
     regulator framework.

  Unfortunately these changes to the core created some breakeage.  We
  think we fixed it all up but for this reason there are lots of last
  minute commits trying to undo the damage"

* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
  clk: Only recalculate the rate if needed
  Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
  clk: qoriq: Add support for the platform PLL
  powerpc/corenet: Enable CLK_QORIQ
  clk: Replace explicit clk assignment with __clk_hw_set_clk
  clk: Add __clk_hw_set_clk helper function
  clk: Don't dereference parent clock if is NULL
  MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
  clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
  clk: shmobile: div6: Avoid division by zero in .round_rate()
  clk: mxs: Fix invalid 32-bit access to frac registers
  clk: omap: compile legacy omap3 clocks conditionally
  clkdev: Export clk_register_clkdev
  clk: Add rate constraints to clocks
  clk: remove clk-private.h
  pci: xgene: do not use clk-private.h
  arm: omap2+ remove dead clock code
  clk: Make clk API return per-user struct clk instances
  clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
  clk: tegra: Add support for the Tegra132 CAR IP block
  ...

1 files changed, 64 insertions, 32 deletions

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index dd34527293e4..382ebd137ee4 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -119,11 +119,19 @@
                 };
 
                 /* dummy clock until actually implemented */
-                pll6: pll6_clk {
+                pll5: pll5_clk {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
-                        clock-frequency = <600000000>;
-                        clock-output-names = "pll6";
+                        clock-frequency = <0>;
+                        clock-output-names = "pll5";
+                };
+
+                pll6: clk@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6", "pll6x2";
                 };
 
                 cpu: cpu_clk@01c20050 {
@@ -149,19 +157,11 @@
                         clock-output-names = "axi";
                 };
 
-                ahb1_mux: ahb1_mux_clk@01c20054 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
-                        reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
-                        clock-output-names = "ahb1_mux";
-                };
-
                 ahb1: ahb1_clk@01c20054 {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-ahb-clk";
+                        compatible = "allwinner,sun6i-a31-ahb1-clk";
                         reg = <0x01c20054 0x4>;
-                        clocks = <&ahb1_mux>;
+                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
                         clock-output-names = "ahb1";
                 };
 
@@ -202,7 +202,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                         clock-output-names = "apb2";
                 };
 
@@ -218,27 +218,41 @@
                 };
 
                 mmc0_clk: clk@01c20088 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20088 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
-                        clock-output-names = "mmc0";
+                        clocks = <&osc24M>, <&pll6 0>;
+                        clock-output-names = "mmc0",
+                                             "mmc0_output",
+                                             "mmc0_sample";
                 };
 
                 mmc1_clk: clk@01c2008c {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c2008c 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
-                        clock-output-names = "mmc1";
+                        clocks = <&osc24M>, <&pll6 0>;
+                        clock-output-names = "mmc1",
+                                             "mmc1_output",
+                                             "mmc1_sample";
                 };
 
                 mmc2_clk: clk@01c20090 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20090 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
-                        clock-output-names = "mmc2";
+                        clocks = <&osc24M>, <&pll6 0>;
+                        clock-output-names = "mmc2",
+                                             "mmc2_output",
+                                             "mmc2_sample";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun8i-a23-mbus-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+                        clock-output-names = "mbus";
                 };
         };
 
@@ -260,8 +274,14 @@
                 mmc0: mmc@01c0f000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c0f000 0x1000>;
-                        clocks = <&ahb1_gates 8>, <&mmc0_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 8>,
+                                 <&mmc0_clk 0>,
+                                 <&mmc0_clk 1>,
+                                 <&mmc0_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 8>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -271,8 +291,14 @@
                 mmc1: mmc@01c10000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c10000 0x1000>;
-                        clocks = <&ahb1_gates 9>, <&mmc1_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 9>,
+                                 <&mmc1_clk 0>,
+                                 <&mmc1_clk 1>,
+                                 <&mmc1_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 9>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -282,8 +308,14 @@
                 mmc2: mmc@01c11000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c11000 0x1000>;
-                        clocks = <&ahb1_gates 10>, <&mmc2_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 10>,
+                                 <&mmc2_clk 0>,
+                                 <&mmc2_clk 1>,
+                                 <&mmc2_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 10>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;