aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/sun5i-a13.dtsi
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 18:29:04 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 18:29:04 -0400
commitf83ccb93585d1f472c30fa2bbb8b56c23dbdb506 (patch)
tree6548d92ff3f362f590bc96129df3e5cb5170ac02 /arch/arm/boot/dts/sun5i-a13.dtsi
parent930b440cd8256f3861bdb0a59d26efaadac7941a (diff)
parent50b4af414d414af9e4df6f64e613bb0ffe581055 (diff)
Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ...
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a13.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi159
1 files changed, 124 insertions, 35 deletions
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 3490ef9ec603..f01c315bdc4b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -16,6 +16,11 @@
16/ { 16/ {
17 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
18 18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart3;
22 };
23
19 cpus { 24 cpus {
20 #address-cells = <1>; 25 #address-cells = <1>;
21 #size-cells = <0>; 26 #size-cells = <0>;
@@ -47,44 +52,48 @@
47 clock-frequency = <0>; 52 clock-frequency = <0>;
48 }; 53 };
49 54
50 osc24M: osc24M@01c20050 { 55 osc24M: clk@01c20050 {
51 #clock-cells = <0>; 56 #clock-cells = <0>;
52 compatible = "allwinner,sun4i-osc-clk"; 57 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>; 58 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>; 59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
55 }; 61 };
56 62
57 osc32k: osc32k { 63 osc32k: clk@0 {
58 #clock-cells = <0>; 64 #clock-cells = <0>;
59 compatible = "fixed-clock"; 65 compatible = "fixed-clock";
60 clock-frequency = <32768>; 66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
61 }; 68 };
62 69
63 pll1: pll1@01c20000 { 70 pll1: clk@01c20000 {
64 #clock-cells = <0>; 71 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 72 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 73 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 74 clocks = <&osc24M>;
75 clock-output-names = "pll1";
68 }; 76 };
69 77
70 pll4: pll4@01c20018 { 78 pll4: clk@01c20018 {
71 #clock-cells = <0>; 79 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 80 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 81 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 82 clocks = <&osc24M>;
83 clock-output-names = "pll4";
75 }; 84 };
76 85
77 pll5: pll5@01c20020 { 86 pll5: clk@01c20020 {
78 #clock-cells = <1>; 87 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 88 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 89 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 90 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 91 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 92 };
84 93
85 pll6: pll6@01c20028 { 94 pll6: clk@01c20028 {
86 #clock-cells = <1>; 95 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 96 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 97 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 98 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +102,23 @@
93 /* dummy is 200M */ 102 /* dummy is 200M */
94 cpu: cpu@01c20054 { 103 cpu: cpu@01c20054 {
95 #clock-cells = <0>; 104 #clock-cells = <0>;
96 compatible = "allwinner,sun4i-cpu-clk"; 105 compatible = "allwinner,sun4i-a10-cpu-clk";
97 reg = <0x01c20054 0x4>; 106 reg = <0x01c20054 0x4>;
98 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu";
99 }; 109 };
100 110
101 axi: axi@01c20054 { 111 axi: axi@01c20054 {
102 #clock-cells = <0>; 112 #clock-cells = <0>;
103 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
104 reg = <0x01c20054 0x4>; 114 reg = <0x01c20054 0x4>;
105 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi";
106 }; 117 };
107 118
108 axi_gates: axi_gates@01c2005c { 119 axi_gates: clk@01c2005c {
109 #clock-cells = <1>; 120 #clock-cells = <1>;
110 compatible = "allwinner,sun4i-axi-gates-clk"; 121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
111 reg = <0x01c2005c 0x4>; 122 reg = <0x01c2005c 0x4>;
112 clocks = <&axi>; 123 clocks = <&axi>;
113 clock-output-names = "axi_dram"; 124 clock-output-names = "axi_dram";
@@ -115,12 +126,13 @@
115 126
116 ahb: ahb@01c20054 { 127 ahb: ahb@01c20054 {
117 #clock-cells = <0>; 128 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
120 clocks = <&axi>; 131 clocks = <&axi>;
132 clock-output-names = "ahb";
121 }; 133 };
122 134
123 ahb_gates: ahb_gates@01c20060 { 135 ahb_gates: clk@01c20060 {
124 #clock-cells = <1>; 136 #clock-cells = <1>;
125 compatible = "allwinner,sun5i-a13-ahb-gates-clk"; 137 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
126 reg = <0x01c20060 0x8>; 138 reg = <0x01c20060 0x8>;
@@ -135,12 +147,13 @@
135 147
136 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
137 #clock-cells = <0>; 149 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
139 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
140 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0";
141 }; 154 };
142 155
143 apb0_gates: apb0_gates@01c20068 { 156 apb0_gates: clk@01c20068 {
144 #clock-cells = <1>; 157 #clock-cells = <1>;
145 compatible = "allwinner,sun5i-a13-apb0-gates-clk"; 158 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
146 reg = <0x01c20068 0x4>; 159 reg = <0x01c20068 0x4>;
@@ -150,19 +163,21 @@
150 163
151 apb1_mux: apb1_mux@01c20058 { 164 apb1_mux: apb1_mux@01c20058 {
152 #clock-cells = <0>; 165 #clock-cells = <0>;
153 compatible = "allwinner,sun4i-apb1-mux-clk"; 166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
154 reg = <0x01c20058 0x4>; 167 reg = <0x01c20058 0x4>;
155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux";
156 }; 170 };
157 171
158 apb1: apb1@01c20058 { 172 apb1: apb1@01c20058 {
159 #clock-cells = <0>; 173 #clock-cells = <0>;
160 compatible = "allwinner,sun4i-apb1-clk"; 174 compatible = "allwinner,sun4i-a10-apb1-clk";
161 reg = <0x01c20058 0x4>; 175 reg = <0x01c20058 0x4>;
162 clocks = <&apb1_mux>; 176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1";
163 }; 178 };
164 179
165 apb1_gates: apb1_gates@01c2006c { 180 apb1_gates: clk@01c2006c {
166 #clock-cells = <1>; 181 #clock-cells = <1>;
167 compatible = "allwinner,sun5i-a13-apb1-gates-clk"; 182 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
168 reg = <0x01c2006c 0x4>; 183 reg = <0x01c2006c 0x4>;
@@ -173,7 +188,7 @@
173 188
174 nand_clk: clk@01c20080 { 189 nand_clk: clk@01c20080 {
175 #clock-cells = <0>; 190 #clock-cells = <0>;
176 compatible = "allwinner,sun4i-mod0-clk"; 191 compatible = "allwinner,sun4i-a10-mod0-clk";
177 reg = <0x01c20080 0x4>; 192 reg = <0x01c20080 0x4>;
178 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
179 clock-output-names = "nand"; 194 clock-output-names = "nand";
@@ -181,7 +196,7 @@
181 196
182 ms_clk: clk@01c20084 { 197 ms_clk: clk@01c20084 {
183 #clock-cells = <0>; 198 #clock-cells = <0>;
184 compatible = "allwinner,sun4i-mod0-clk"; 199 compatible = "allwinner,sun4i-a10-mod0-clk";
185 reg = <0x01c20084 0x4>; 200 reg = <0x01c20084 0x4>;
186 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187 clock-output-names = "ms"; 202 clock-output-names = "ms";
@@ -189,7 +204,7 @@
189 204
190 mmc0_clk: clk@01c20088 { 205 mmc0_clk: clk@01c20088 {
191 #clock-cells = <0>; 206 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk"; 207 compatible = "allwinner,sun4i-a10-mod0-clk";
193 reg = <0x01c20088 0x4>; 208 reg = <0x01c20088 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "mmc0"; 210 clock-output-names = "mmc0";
@@ -197,7 +212,7 @@
197 212
198 mmc1_clk: clk@01c2008c { 213 mmc1_clk: clk@01c2008c {
199 #clock-cells = <0>; 214 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk"; 215 compatible = "allwinner,sun4i-a10-mod0-clk";
201 reg = <0x01c2008c 0x4>; 216 reg = <0x01c2008c 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "mmc1"; 218 clock-output-names = "mmc1";
@@ -205,7 +220,7 @@
205 220
206 mmc2_clk: clk@01c20090 { 221 mmc2_clk: clk@01c20090 {
207 #clock-cells = <0>; 222 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk"; 223 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20090 0x4>; 224 reg = <0x01c20090 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc2"; 226 clock-output-names = "mmc2";
@@ -213,7 +228,7 @@
213 228
214 ts_clk: clk@01c20098 { 229 ts_clk: clk@01c20098 {
215 #clock-cells = <0>; 230 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk"; 231 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c20098 0x4>; 232 reg = <0x01c20098 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ts"; 234 clock-output-names = "ts";
@@ -221,7 +236,7 @@
221 236
222 ss_clk: clk@01c2009c { 237 ss_clk: clk@01c2009c {
223 #clock-cells = <0>; 238 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk"; 239 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c2009c 0x4>; 240 reg = <0x01c2009c 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "ss"; 242 clock-output-names = "ss";
@@ -229,7 +244,7 @@
229 244
230 spi0_clk: clk@01c200a0 { 245 spi0_clk: clk@01c200a0 {
231 #clock-cells = <0>; 246 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk"; 247 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c200a0 0x4>; 248 reg = <0x01c200a0 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "spi0"; 250 clock-output-names = "spi0";
@@ -237,7 +252,7 @@
237 252
238 spi1_clk: clk@01c200a4 { 253 spi1_clk: clk@01c200a4 {
239 #clock-cells = <0>; 254 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk"; 255 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c200a4 0x4>; 256 reg = <0x01c200a4 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "spi1"; 258 clock-output-names = "spi1";
@@ -245,7 +260,7 @@
245 260
246 spi2_clk: clk@01c200a8 { 261 spi2_clk: clk@01c200a8 {
247 #clock-cells = <0>; 262 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk"; 263 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c200a8 0x4>; 264 reg = <0x01c200a8 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "spi2"; 266 clock-output-names = "spi2";
@@ -253,15 +268,24 @@
253 268
254 ir0_clk: clk@01c200b0 { 269 ir0_clk: clk@01c200b0 {
255 #clock-cells = <0>; 270 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c200b0 0x4>; 272 reg = <0x01c200b0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ir0"; 274 clock-output-names = "ir0";
260 }; 275 };
261 276
277 usb_clk: clk@01c200cc {
278 #clock-cells = <1>;
279 #reset-cells = <1>;
280 compatible = "allwinner,sun5i-a13-usb-clk";
281 reg = <0x01c200cc 0x4>;
282 clocks = <&pll6 1>;
283 clock-output-names = "usb_ohci0", "usb_phy";
284 };
285
262 mbus_clk: clk@01c2015c { 286 mbus_clk: clk@01c2015c {
263 #clock-cells = <0>; 287 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c2015c 0x4>; 289 reg = <0x01c2015c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "mbus"; 291 clock-output-names = "mbus";
@@ -274,6 +298,71 @@
274 #size-cells = <1>; 298 #size-cells = <1>;
275 ranges; 299 ranges;
276 300
301 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
304 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 spi1: spi@01c06000 {
313 compatible = "allwinner,sun4i-a10-spi";
314 reg = <0x01c06000 0x1000>;
315 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
322
323 usbphy: phy@01c13400 {
324 #phy-cells = <1>;
325 compatible = "allwinner,sun5i-a13-usb-phy";
326 reg = <0x01c13400 0x10 0x01c14800 0x4>;
327 reg-names = "phy_ctrl", "pmu1";
328 clocks = <&usb_clk 8>;
329 clock-names = "usb_phy";
330 resets = <&usb_clk 1>;
331 reset-names = "usb1_reset";
332 status = "disabled";
333 };
334
335 ehci0: usb@01c14000 {
336 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
337 reg = <0x01c14000 0x100>;
338 interrupts = <39>;
339 clocks = <&ahb_gates 1>;
340 phys = <&usbphy 1>;
341 phy-names = "usb";
342 status = "disabled";
343 };
344
345 ohci0: usb@01c14400 {
346 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
347 reg = <0x01c14400 0x100>;
348 interrupts = <40>;
349 clocks = <&usb_clk 6>, <&ahb_gates 2>;
350 phys = <&usbphy 1>;
351 phy-names = "usb";
352 status = "disabled";
353 };
354
355 spi2: spi@01c17000 {
356 compatible = "allwinner,sun4i-a10-spi";
357 reg = <0x01c17000 0x1000>;
358 interrupts = <12>;
359 clocks = <&ahb_gates 22>, <&spi2_clk>;
360 clock-names = "ahb", "mod";
361 status = "disabled";
362 #address-cells = <1>;
363 #size-cells = <0>;
364 };
365
277 intc: interrupt-controller@01c20400 { 366 intc: interrupt-controller@01c20400 {
278 compatible = "allwinner,sun4i-a10-ic"; 367 compatible = "allwinner,sun4i-a10-ic";
279 reg = <0x01c20400 0x400>; 368 reg = <0x01c20400 0x400>;
@@ -336,7 +425,7 @@
336 }; 425 };
337 426
338 wdt: watchdog@01c20c90 { 427 wdt: watchdog@01c20c90 {
339 compatible = "allwinner,sun4i-wdt"; 428 compatible = "allwinner,sun4i-a10-wdt";
340 reg = <0x01c20c90 0x10>; 429 reg = <0x01c20c90 0x10>;
341 }; 430 };
342 431
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-10 02:35:31 -0500