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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-06 03:55:58 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-18 10:53:37 -0500
commitbf6534a180d6d596521b0bfa6de29da5e18314a6 (patch)
treeb242fff5bb0993c718fe6a6daa21935d003efb91 /arch/arm/boot/dts/sun5i-a13.dtsi
parent7902763e4a4d04a96406447f935a8f676e73e0ce (diff)
ARM: sunxi: dt: Convert to the new clock compatibles
Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a13.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index b1468b3c7c57..6caf65dbf187 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -54,7 +54,7 @@
54 54
55 osc24M: clk@01c20050 { 55 osc24M: clk@01c20050 {
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 compatible = "allwinner,sun4i-osc-clk"; 57 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>; 58 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>; 59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M"; 60 clock-output-names = "osc24M";
@@ -69,7 +69,7 @@
69 69
70 pll1: clk@01c20000 { 70 pll1: clk@01c20000 {
71 #clock-cells = <0>; 71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 72 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20000 0x4>; 73 reg = <0x01c20000 0x4>;
74 clocks = <&osc24M>; 74 clocks = <&osc24M>;
75 clock-output-names = "pll1"; 75 clock-output-names = "pll1";
@@ -77,7 +77,7 @@
77 77
78 pll4: clk@01c20018 { 78 pll4: clk@01c20018 {
79 #clock-cells = <0>; 79 #clock-cells = <0>;
80 compatible = "allwinner,sun4i-pll1-clk"; 80 compatible = "allwinner,sun4i-a10-pll1-clk";
81 reg = <0x01c20018 0x4>; 81 reg = <0x01c20018 0x4>;
82 clocks = <&osc24M>; 82 clocks = <&osc24M>;
83 clock-output-names = "pll4"; 83 clock-output-names = "pll4";
@@ -85,7 +85,7 @@
85 85
86 pll5: clk@01c20020 { 86 pll5: clk@01c20020 {
87 #clock-cells = <1>; 87 #clock-cells = <1>;
88 compatible = "allwinner,sun4i-pll5-clk"; 88 compatible = "allwinner,sun4i-a10-pll5-clk";
89 reg = <0x01c20020 0x4>; 89 reg = <0x01c20020 0x4>;
90 clocks = <&osc24M>; 90 clocks = <&osc24M>;
91 clock-output-names = "pll5_ddr", "pll5_other"; 91 clock-output-names = "pll5_ddr", "pll5_other";
@@ -93,7 +93,7 @@
93 93
94 pll6: clk@01c20028 { 94 pll6: clk@01c20028 {
95 #clock-cells = <1>; 95 #clock-cells = <1>;
96 compatible = "allwinner,sun4i-pll6-clk"; 96 compatible = "allwinner,sun4i-a10-pll6-clk";
97 reg = <0x01c20028 0x4>; 97 reg = <0x01c20028 0x4>;
98 clocks = <&osc24M>; 98 clocks = <&osc24M>;
99 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -102,7 +102,7 @@
102 /* dummy is 200M */ 102 /* dummy is 200M */
103 cpu: cpu@01c20054 { 103 cpu: cpu@01c20054 {
104 #clock-cells = <0>; 104 #clock-cells = <0>;
105 compatible = "allwinner,sun4i-cpu-clk"; 105 compatible = "allwinner,sun4i-a10-cpu-clk";
106 reg = <0x01c20054 0x4>; 106 reg = <0x01c20054 0x4>;
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu"; 108 clock-output-names = "cpu";
@@ -110,7 +110,7 @@
110 110
111 axi: axi@01c20054 { 111 axi: axi@01c20054 {
112 #clock-cells = <0>; 112 #clock-cells = <0>;
113 compatible = "allwinner,sun4i-axi-clk"; 113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20054 0x4>; 114 reg = <0x01c20054 0x4>;
115 clocks = <&cpu>; 115 clocks = <&cpu>;
116 clock-output-names = "axi"; 116 clock-output-names = "axi";
@@ -118,7 +118,7 @@
118 118
119 axi_gates: clk@01c2005c { 119 axi_gates: clk@01c2005c {
120 #clock-cells = <1>; 120 #clock-cells = <1>;
121 compatible = "allwinner,sun4i-axi-gates-clk"; 121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
122 reg = <0x01c2005c 0x4>; 122 reg = <0x01c2005c 0x4>;
123 clocks = <&axi>; 123 clocks = <&axi>;
124 clock-output-names = "axi_dram"; 124 clock-output-names = "axi_dram";
@@ -126,7 +126,7 @@
126 126
127 ahb: ahb@01c20054 { 127 ahb: ahb@01c20054 {
128 #clock-cells = <0>; 128 #clock-cells = <0>;
129 compatible = "allwinner,sun4i-ahb-clk"; 129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>; 130 reg = <0x01c20054 0x4>;
131 clocks = <&axi>; 131 clocks = <&axi>;
132 clock-output-names = "ahb"; 132 clock-output-names = "ahb";
@@ -147,7 +147,7 @@
147 147
148 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
149 #clock-cells = <0>; 149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0"; 153 clock-output-names = "apb0";
@@ -163,7 +163,7 @@
163 163
164 apb1_mux: apb1_mux@01c20058 { 164 apb1_mux: apb1_mux@01c20058 {
165 #clock-cells = <0>; 165 #clock-cells = <0>;
166 compatible = "allwinner,sun4i-apb1-mux-clk"; 166 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
167 reg = <0x01c20058 0x4>; 167 reg = <0x01c20058 0x4>;
168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1_mux"; 169 clock-output-names = "apb1_mux";
@@ -171,7 +171,7 @@
171 171
172 apb1: apb1@01c20058 { 172 apb1: apb1@01c20058 {
173 #clock-cells = <0>; 173 #clock-cells = <0>;
174 compatible = "allwinner,sun4i-apb1-clk"; 174 compatible = "allwinner,sun4i-a10-apb1-clk";
175 reg = <0x01c20058 0x4>; 175 reg = <0x01c20058 0x4>;
176 clocks = <&apb1_mux>; 176 clocks = <&apb1_mux>;
177 clock-output-names = "apb1"; 177 clock-output-names = "apb1";
@@ -188,7 +188,7 @@
188 188
189 nand_clk: clk@01c20080 { 189 nand_clk: clk@01c20080 {
190 #clock-cells = <0>; 190 #clock-cells = <0>;
191 compatible = "allwinner,sun4i-mod0-clk"; 191 compatible = "allwinner,sun4i-a10-mod0-clk";
192 reg = <0x01c20080 0x4>; 192 reg = <0x01c20080 0x4>;
193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
194 clock-output-names = "nand"; 194 clock-output-names = "nand";
@@ -196,7 +196,7 @@
196 196
197 ms_clk: clk@01c20084 { 197 ms_clk: clk@01c20084 {
198 #clock-cells = <0>; 198 #clock-cells = <0>;
199 compatible = "allwinner,sun4i-mod0-clk"; 199 compatible = "allwinner,sun4i-a10-mod0-clk";
200 reg = <0x01c20084 0x4>; 200 reg = <0x01c20084 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "ms"; 202 clock-output-names = "ms";
@@ -204,7 +204,7 @@
204 204
205 mmc0_clk: clk@01c20088 { 205 mmc0_clk: clk@01c20088 {
206 #clock-cells = <0>; 206 #clock-cells = <0>;
207 compatible = "allwinner,sun4i-mod0-clk"; 207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20088 0x4>; 208 reg = <0x01c20088 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc0"; 210 clock-output-names = "mmc0";
@@ -212,7 +212,7 @@
212 212
213 mmc1_clk: clk@01c2008c { 213 mmc1_clk: clk@01c2008c {
214 #clock-cells = <0>; 214 #clock-cells = <0>;
215 compatible = "allwinner,sun4i-mod0-clk"; 215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c2008c 0x4>; 216 reg = <0x01c2008c 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc1"; 218 clock-output-names = "mmc1";
@@ -220,7 +220,7 @@
220 220
221 mmc2_clk: clk@01c20090 { 221 mmc2_clk: clk@01c20090 {
222 #clock-cells = <0>; 222 #clock-cells = <0>;
223 compatible = "allwinner,sun4i-mod0-clk"; 223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c20090 0x4>; 224 reg = <0x01c20090 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc2"; 226 clock-output-names = "mmc2";
@@ -228,7 +228,7 @@
228 228
229 ts_clk: clk@01c20098 { 229 ts_clk: clk@01c20098 {
230 #clock-cells = <0>; 230 #clock-cells = <0>;
231 compatible = "allwinner,sun4i-mod0-clk"; 231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c20098 0x4>; 232 reg = <0x01c20098 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "ts"; 234 clock-output-names = "ts";
@@ -236,7 +236,7 @@
236 236
237 ss_clk: clk@01c2009c { 237 ss_clk: clk@01c2009c {
238 #clock-cells = <0>; 238 #clock-cells = <0>;
239 compatible = "allwinner,sun4i-mod0-clk"; 239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c2009c 0x4>; 240 reg = <0x01c2009c 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "ss"; 242 clock-output-names = "ss";
@@ -244,7 +244,7 @@
244 244
245 spi0_clk: clk@01c200a0 { 245 spi0_clk: clk@01c200a0 {
246 #clock-cells = <0>; 246 #clock-cells = <0>;
247 compatible = "allwinner,sun4i-mod0-clk"; 247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c200a0 0x4>; 248 reg = <0x01c200a0 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "spi0"; 250 clock-output-names = "spi0";
@@ -252,7 +252,7 @@
252 252
253 spi1_clk: clk@01c200a4 { 253 spi1_clk: clk@01c200a4 {
254 #clock-cells = <0>; 254 #clock-cells = <0>;
255 compatible = "allwinner,sun4i-mod0-clk"; 255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a4 0x4>; 256 reg = <0x01c200a4 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi1"; 258 clock-output-names = "spi1";
@@ -260,7 +260,7 @@
260 260
261 spi2_clk: clk@01c200a8 { 261 spi2_clk: clk@01c200a8 {
262 #clock-cells = <0>; 262 #clock-cells = <0>;
263 compatible = "allwinner,sun4i-mod0-clk"; 263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a8 0x4>; 264 reg = <0x01c200a8 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi2"; 266 clock-output-names = "spi2";
@@ -268,7 +268,7 @@
268 268
269 ir0_clk: clk@01c200b0 { 269 ir0_clk: clk@01c200b0 {
270 #clock-cells = <0>; 270 #clock-cells = <0>;
271 compatible = "allwinner,sun4i-mod0-clk"; 271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200b0 0x4>; 272 reg = <0x01c200b0 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "ir0"; 274 clock-output-names = "ir0";
@@ -285,7 +285,7 @@
285 285
286 mbus_clk: clk@01c2015c { 286 mbus_clk: clk@01c2015c {
287 #clock-cells = <0>; 287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c2015c 0x4>; 289 reg = <0x01c2015c 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "mbus"; 291 clock-output-names = "mbus";
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-05 01:04:22 -0500