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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-22 16:35:57 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-24 04:02:49 -0500
commit8f8658b713b29d1507da2294883b5b37a85e714e (patch)
tree54412bb65079693056503f43c5641e4a00348610 /arch/arm/boot/dts/sun5i-a13.dtsi
parent8a689569b13055ca40df4e88f4f3140bd5614825 (diff)
ARM: dt: sun5i: Add A13 SPI controller nodes
The A13 has 3 SPI controllers compatible with the one found in the A10. Add them in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a13.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 6caf65dbf187..cda1d4bbe2e2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -298,6 +298,39 @@
298 #size-cells = <1>; 298 #size-cells = <1>;
299 ranges; 299 ranges;
300 300
301 spi0: spi@01c05000 {
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
304 interrupts = <10>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 status = "disabled";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 };
311
312 spi1: spi@01c06000 {
313 compatible = "allwinner,sun4i-a10-spi";
314 reg = <0x01c06000 0x1000>;
315 interrupts = <11>;
316 clocks = <&ahb_gates 21>, <&spi1_clk>;
317 clock-names = "ahb", "mod";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 };
322
323 spi2: spi@01c17000 {
324 compatible = "allwinner,sun4i-a10-spi";
325 reg = <0x01c17000 0x1000>;
326 interrupts = <12>;
327 clocks = <&ahb_gates 22>, <&spi2_clk>;
328 clock-names = "ahb", "mod";
329 status = "disabled";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 };
333
301 intc: interrupt-controller@01c20400 { 334 intc: interrupt-controller@01c20400 {
302 compatible = "allwinner,sun4i-ic"; 335 compatible = "allwinner,sun4i-ic";
303 reg = <0x01c20400 0x400>; 336 reg = <0x01c20400 0x400>;