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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 18:29:04 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-05 18:29:04 -0400
commitf83ccb93585d1f472c30fa2bbb8b56c23dbdb506 (patch)
tree6548d92ff3f362f590bc96129df3e5cb5170ac02 /arch/arm/boot/dts/sun5i-a10s.dtsi
parent930b440cd8256f3861bdb0a59d26efaadac7941a (diff)
parent50b4af414d414af9e4df6f64e613bb0ffe581055 (diff)
Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ...
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a10s.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi158
1 files changed, 123 insertions, 35 deletions
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ee17b1c379e3..79989ed5658d 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -18,6 +18,10 @@
18 18
19 aliases { 19 aliases {
20 ethernet0 = &emac; 20 ethernet0 = &emac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
21 }; 25 };
22 26
23 cpus { 27 cpus {
@@ -47,44 +51,48 @@
47 clock-frequency = <0>; 51 clock-frequency = <0>;
48 }; 52 };
49 53
50 osc24M: osc24M@01c20050 { 54 osc24M: clk@01c20050 {
51 #clock-cells = <0>; 55 #clock-cells = <0>;
52 compatible = "allwinner,sun4i-osc-clk"; 56 compatible = "allwinner,sun4i-a10-osc-clk";
53 reg = <0x01c20050 0x4>; 57 reg = <0x01c20050 0x4>;
54 clock-frequency = <24000000>; 58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M";
55 }; 60 };
56 61
57 osc32k: osc32k { 62 osc32k: clk@0 {
58 #clock-cells = <0>; 63 #clock-cells = <0>;
59 compatible = "fixed-clock"; 64 compatible = "fixed-clock";
60 clock-frequency = <32768>; 65 clock-frequency = <32768>;
66 clock-output-names = "osc32k";
61 }; 67 };
62 68
63 pll1: pll1@01c20000 { 69 pll1: clk@01c20000 {
64 #clock-cells = <0>; 70 #clock-cells = <0>;
65 compatible = "allwinner,sun4i-pll1-clk"; 71 compatible = "allwinner,sun4i-a10-pll1-clk";
66 reg = <0x01c20000 0x4>; 72 reg = <0x01c20000 0x4>;
67 clocks = <&osc24M>; 73 clocks = <&osc24M>;
74 clock-output-names = "pll1";
68 }; 75 };
69 76
70 pll4: pll4@01c20018 { 77 pll4: clk@01c20018 {
71 #clock-cells = <0>; 78 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk"; 79 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20018 0x4>; 80 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>; 81 clocks = <&osc24M>;
82 clock-output-names = "pll4";
75 }; 83 };
76 84
77 pll5: pll5@01c20020 { 85 pll5: clk@01c20020 {
78 #clock-cells = <1>; 86 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk"; 87 compatible = "allwinner,sun4i-a10-pll5-clk";
80 reg = <0x01c20020 0x4>; 88 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>; 89 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other"; 90 clock-output-names = "pll5_ddr", "pll5_other";
83 }; 91 };
84 92
85 pll6: pll6@01c20028 { 93 pll6: clk@01c20028 {
86 #clock-cells = <1>; 94 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk"; 95 compatible = "allwinner,sun4i-a10-pll6-clk";
88 reg = <0x01c20028 0x4>; 96 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>; 97 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -93,21 +101,23 @@
93 /* dummy is 200M */ 101 /* dummy is 200M */
94 cpu: cpu@01c20054 { 102 cpu: cpu@01c20054 {
95 #clock-cells = <0>; 103 #clock-cells = <0>;
96 compatible = "allwinner,sun4i-cpu-clk"; 104 compatible = "allwinner,sun4i-a10-cpu-clk";
97 reg = <0x01c20054 0x4>; 105 reg = <0x01c20054 0x4>;
98 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu";
99 }; 108 };
100 109
101 axi: axi@01c20054 { 110 axi: axi@01c20054 {
102 #clock-cells = <0>; 111 #clock-cells = <0>;
103 compatible = "allwinner,sun4i-axi-clk"; 112 compatible = "allwinner,sun4i-a10-axi-clk";
104 reg = <0x01c20054 0x4>; 113 reg = <0x01c20054 0x4>;
105 clocks = <&cpu>; 114 clocks = <&cpu>;
115 clock-output-names = "axi";
106 }; 116 };
107 117
108 axi_gates: axi_gates@01c2005c { 118 axi_gates: clk@01c2005c {
109 #clock-cells = <1>; 119 #clock-cells = <1>;
110 compatible = "allwinner,sun4i-axi-gates-clk"; 120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
111 reg = <0x01c2005c 0x4>; 121 reg = <0x01c2005c 0x4>;
112 clocks = <&axi>; 122 clocks = <&axi>;
113 clock-output-names = "axi_dram"; 123 clock-output-names = "axi_dram";
@@ -115,12 +125,13 @@
115 125
116 ahb: ahb@01c20054 { 126 ahb: ahb@01c20054 {
117 #clock-cells = <0>; 127 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk"; 128 compatible = "allwinner,sun4i-a10-ahb-clk";
119 reg = <0x01c20054 0x4>; 129 reg = <0x01c20054 0x4>;
120 clocks = <&axi>; 130 clocks = <&axi>;
131 clock-output-names = "ahb";
121 }; 132 };
122 133
123 ahb_gates: ahb_gates@01c20060 { 134 ahb_gates: clk@01c20060 {
124 #clock-cells = <1>; 135 #clock-cells = <1>;
125 compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; 136 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
126 reg = <0x01c20060 0x8>; 137 reg = <0x01c20060 0x8>;
@@ -136,12 +147,13 @@
136 147
137 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
138 #clock-cells = <0>; 149 #clock-cells = <0>;
139 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
140 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
141 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0";
142 }; 154 };
143 155
144 apb0_gates: apb0_gates@01c20068 { 156 apb0_gates: clk@01c20068 {
145 #clock-cells = <1>; 157 #clock-cells = <1>;
146 compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; 158 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
147 reg = <0x01c20068 0x4>; 159 reg = <0x01c20068 0x4>;
@@ -152,19 +164,21 @@
152 164
153 apb1_mux: apb1_mux@01c20058 { 165 apb1_mux: apb1_mux@01c20058 {
154 #clock-cells = <0>; 166 #clock-cells = <0>;
155 compatible = "allwinner,sun4i-apb1-mux-clk"; 167 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
156 reg = <0x01c20058 0x4>; 168 reg = <0x01c20058 0x4>;
157 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1_mux";
158 }; 171 };
159 172
160 apb1: apb1@01c20058 { 173 apb1: apb1@01c20058 {
161 #clock-cells = <0>; 174 #clock-cells = <0>;
162 compatible = "allwinner,sun4i-apb1-clk"; 175 compatible = "allwinner,sun4i-a10-apb1-clk";
163 reg = <0x01c20058 0x4>; 176 reg = <0x01c20058 0x4>;
164 clocks = <&apb1_mux>; 177 clocks = <&apb1_mux>;
178 clock-output-names = "apb1";
165 }; 179 };
166 180
167 apb1_gates: apb1_gates@01c2006c { 181 apb1_gates: clk@01c2006c {
168 #clock-cells = <1>; 182 #clock-cells = <1>;
169 compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; 183 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
170 reg = <0x01c2006c 0x4>; 184 reg = <0x01c2006c 0x4>;
@@ -176,7 +190,7 @@
176 190
177 nand_clk: clk@01c20080 { 191 nand_clk: clk@01c20080 {
178 #clock-cells = <0>; 192 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-mod0-clk"; 193 compatible = "allwinner,sun4i-a10-mod0-clk";
180 reg = <0x01c20080 0x4>; 194 reg = <0x01c20080 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
182 clock-output-names = "nand"; 196 clock-output-names = "nand";
@@ -184,7 +198,7 @@
184 198
185 ms_clk: clk@01c20084 { 199 ms_clk: clk@01c20084 {
186 #clock-cells = <0>; 200 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-mod0-clk"; 201 compatible = "allwinner,sun4i-a10-mod0-clk";
188 reg = <0x01c20084 0x4>; 202 reg = <0x01c20084 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "ms"; 204 clock-output-names = "ms";
@@ -192,7 +206,7 @@
192 206
193 mmc0_clk: clk@01c20088 { 207 mmc0_clk: clk@01c20088 {
194 #clock-cells = <0>; 208 #clock-cells = <0>;
195 compatible = "allwinner,sun4i-mod0-clk"; 209 compatible = "allwinner,sun4i-a10-mod0-clk";
196 reg = <0x01c20088 0x4>; 210 reg = <0x01c20088 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "mmc0"; 212 clock-output-names = "mmc0";
@@ -200,7 +214,7 @@
200 214
201 mmc1_clk: clk@01c2008c { 215 mmc1_clk: clk@01c2008c {
202 #clock-cells = <0>; 216 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-mod0-clk"; 217 compatible = "allwinner,sun4i-a10-mod0-clk";
204 reg = <0x01c2008c 0x4>; 218 reg = <0x01c2008c 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "mmc1"; 220 clock-output-names = "mmc1";
@@ -208,7 +222,7 @@
208 222
209 mmc2_clk: clk@01c20090 { 223 mmc2_clk: clk@01c20090 {
210 #clock-cells = <0>; 224 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-mod0-clk"; 225 compatible = "allwinner,sun4i-a10-mod0-clk";
212 reg = <0x01c20090 0x4>; 226 reg = <0x01c20090 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc2"; 228 clock-output-names = "mmc2";
@@ -216,7 +230,7 @@
216 230
217 ts_clk: clk@01c20098 { 231 ts_clk: clk@01c20098 {
218 #clock-cells = <0>; 232 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-mod0-clk"; 233 compatible = "allwinner,sun4i-a10-mod0-clk";
220 reg = <0x01c20098 0x4>; 234 reg = <0x01c20098 0x4>;
221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
222 clock-output-names = "ts"; 236 clock-output-names = "ts";
@@ -224,7 +238,7 @@
224 238
225 ss_clk: clk@01c2009c { 239 ss_clk: clk@01c2009c {
226 #clock-cells = <0>; 240 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-mod0-clk"; 241 compatible = "allwinner,sun4i-a10-mod0-clk";
228 reg = <0x01c2009c 0x4>; 242 reg = <0x01c2009c 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
230 clock-output-names = "ss"; 244 clock-output-names = "ss";
@@ -232,7 +246,7 @@
232 246
233 spi0_clk: clk@01c200a0 { 247 spi0_clk: clk@01c200a0 {
234 #clock-cells = <0>; 248 #clock-cells = <0>;
235 compatible = "allwinner,sun4i-mod0-clk"; 249 compatible = "allwinner,sun4i-a10-mod0-clk";
236 reg = <0x01c200a0 0x4>; 250 reg = <0x01c200a0 0x4>;
237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
238 clock-output-names = "spi0"; 252 clock-output-names = "spi0";
@@ -240,7 +254,7 @@
240 254
241 spi1_clk: clk@01c200a4 { 255 spi1_clk: clk@01c200a4 {
242 #clock-cells = <0>; 256 #clock-cells = <0>;
243 compatible = "allwinner,sun4i-mod0-clk"; 257 compatible = "allwinner,sun4i-a10-mod0-clk";
244 reg = <0x01c200a4 0x4>; 258 reg = <0x01c200a4 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "spi1"; 260 clock-output-names = "spi1";
@@ -248,7 +262,7 @@
248 262
249 spi2_clk: clk@01c200a8 { 263 spi2_clk: clk@01c200a8 {
250 #clock-cells = <0>; 264 #clock-cells = <0>;
251 compatible = "allwinner,sun4i-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mod0-clk";
252 reg = <0x01c200a8 0x4>; 266 reg = <0x01c200a8 0x4>;
253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
254 clock-output-names = "spi2"; 268 clock-output-names = "spi2";
@@ -256,15 +270,24 @@
256 270
257 ir0_clk: clk@01c200b0 { 271 ir0_clk: clk@01c200b0 {
258 #clock-cells = <0>; 272 #clock-cells = <0>;
259 compatible = "allwinner,sun4i-mod0-clk"; 273 compatible = "allwinner,sun4i-a10-mod0-clk";
260 reg = <0x01c200b0 0x4>; 274 reg = <0x01c200b0 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "ir0"; 276 clock-output-names = "ir0";
263 }; 277 };
264 278
279 usb_clk: clk@01c200cc {
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 compatible = "allwinner,sun5i-a13-usb-clk";
283 reg = <0x01c200cc 0x4>;
284 clocks = <&pll6 1>;
285 clock-output-names = "usb_ohci0", "usb_phy";
286 };
287
265 mbus_clk: clk@01c2015c { 288 mbus_clk: clk@01c2015c {
266 #clock-cells = <0>; 289 #clock-cells = <0>;
267 compatible = "allwinner,sun4i-mod0-clk"; 290 compatible = "allwinner,sun4i-a10-mod0-clk";
268 reg = <0x01c2015c 0x4>; 291 reg = <0x01c2015c 0x4>;
269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
270 clock-output-names = "mbus"; 293 clock-output-names = "mbus";
@@ -277,6 +300,28 @@
277 #size-cells = <1>; 300 #size-cells = <1>;
278 ranges; 301 ranges;
279 302
303 spi0: spi@01c05000 {
304 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>;
306 interrupts = <10>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod";
309 status = "disabled";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 };
313
314 spi1: spi@01c06000 {
315 compatible = "allwinner,sun4i-a10-spi";
316 reg = <0x01c06000 0x1000>;
317 interrupts = <11>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod";
320 status = "disabled";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
324
280 emac: ethernet@01c0b000 { 325 emac: ethernet@01c0b000 {
281 compatible = "allwinner,sun4i-a10-emac"; 326 compatible = "allwinner,sun4i-a10-emac";
282 reg = <0x01c0b000 0x1000>; 327 reg = <0x01c0b000 0x1000>;
@@ -293,6 +338,49 @@
293 #size-cells = <0>; 338 #size-cells = <0>;
294 }; 339 };
295 340
341 usbphy: phy@01c13400 {
342 #phy-cells = <1>;
343 compatible = "allwinner,sun5i-a13-usb-phy";
344 reg = <0x01c13400 0x10 0x01c14800 0x4>;
345 reg-names = "phy_ctrl", "pmu1";
346 clocks = <&usb_clk 8>;
347 clock-names = "usb_phy";
348 resets = <&usb_clk 1>;
349 reset-names = "usb1_reset";
350 status = "disabled";
351 };
352
353 ehci0: usb@01c14000 {
354 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
355 reg = <0x01c14000 0x100>;
356 interrupts = <39>;
357 clocks = <&ahb_gates 1>;
358 phys = <&usbphy 1>;
359 phy-names = "usb";
360 status = "disabled";
361 };
362
363 ohci0: usb@01c14400 {
364 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
365 reg = <0x01c14400 0x100>;
366 interrupts = <40>;
367 clocks = <&usb_clk 6>, <&ahb_gates 2>;
368 phys = <&usbphy 1>;
369 phy-names = "usb";
370 status = "disabled";
371 };
372
373 spi2: spi@01c17000 {
374 compatible = "allwinner,sun4i-a10-spi";
375 reg = <0x01c17000 0x1000>;
376 interrupts = <12>;
377 clocks = <&ahb_gates 22>, <&spi2_clk>;
378 clock-names = "ahb", "mod";
379 status = "disabled";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
383
296 intc: interrupt-controller@01c20400 { 384 intc: interrupt-controller@01c20400 {
297 compatible = "allwinner,sun4i-a10-ic"; 385 compatible = "allwinner,sun4i-a10-ic";
298 reg = <0x01c20400 0x400>; 386 reg = <0x01c20400 0x400>;
@@ -373,7 +461,7 @@
373 }; 461 };
374 462
375 wdt: watchdog@01c20c90 { 463 wdt: watchdog@01c20c90 {
376 compatible = "allwinner,sun4i-wdt"; 464 compatible = "allwinner,sun4i-a10-wdt";
377 reg = <0x01c20c90 0x10>; 465 reg = <0x01c20c90 0x10>;
378 }; 466 };
379 467
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-08 03:46:40 -0500