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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-06 03:55:58 -0500
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-02-18 10:53:37 -0500
commitbf6534a180d6d596521b0bfa6de29da5e18314a6 (patch)
treeb242fff5bb0993c718fe6a6daa21935d003efb91 /arch/arm/boot/dts/sun5i-a10s.dtsi
parent7902763e4a4d04a96406447f935a8f676e73e0ce (diff)
ARM: sunxi: dt: Convert to the new clock compatibles
Switch the device tree to the new compatibles introduced in the clock drivers to have a common pattern accross all Allwinner SoCs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a10s.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0e0da137279f..9cbd88421dbc 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -53,7 +53,7 @@
53 53
54 osc24M: clk@01c20050 { 54 osc24M: clk@01c20050 {
55 #clock-cells = <0>; 55 #clock-cells = <0>;
56 compatible = "allwinner,sun4i-osc-clk"; 56 compatible = "allwinner,sun4i-a10-osc-clk";
57 reg = <0x01c20050 0x4>; 57 reg = <0x01c20050 0x4>;
58 clock-frequency = <24000000>; 58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M"; 59 clock-output-names = "osc24M";
@@ -68,7 +68,7 @@
68 68
69 pll1: clk@01c20000 { 69 pll1: clk@01c20000 {
70 #clock-cells = <0>; 70 #clock-cells = <0>;
71 compatible = "allwinner,sun4i-pll1-clk"; 71 compatible = "allwinner,sun4i-a10-pll1-clk";
72 reg = <0x01c20000 0x4>; 72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>; 73 clocks = <&osc24M>;
74 clock-output-names = "pll1"; 74 clock-output-names = "pll1";
@@ -76,7 +76,7 @@
76 76
77 pll4: clk@01c20018 { 77 pll4: clk@01c20018 {
78 #clock-cells = <0>; 78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-pll1-clk"; 79 compatible = "allwinner,sun4i-a10-pll1-clk";
80 reg = <0x01c20018 0x4>; 80 reg = <0x01c20018 0x4>;
81 clocks = <&osc24M>; 81 clocks = <&osc24M>;
82 clock-output-names = "pll4"; 82 clock-output-names = "pll4";
@@ -84,7 +84,7 @@
84 84
85 pll5: clk@01c20020 { 85 pll5: clk@01c20020 {
86 #clock-cells = <1>; 86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll5-clk"; 87 compatible = "allwinner,sun4i-a10-pll5-clk";
88 reg = <0x01c20020 0x4>; 88 reg = <0x01c20020 0x4>;
89 clocks = <&osc24M>; 89 clocks = <&osc24M>;
90 clock-output-names = "pll5_ddr", "pll5_other"; 90 clock-output-names = "pll5_ddr", "pll5_other";
@@ -92,7 +92,7 @@
92 92
93 pll6: clk@01c20028 { 93 pll6: clk@01c20028 {
94 #clock-cells = <1>; 94 #clock-cells = <1>;
95 compatible = "allwinner,sun4i-pll6-clk"; 95 compatible = "allwinner,sun4i-a10-pll6-clk";
96 reg = <0x01c20028 0x4>; 96 reg = <0x01c20028 0x4>;
97 clocks = <&osc24M>; 97 clocks = <&osc24M>;
98 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -101,7 +101,7 @@
101 /* dummy is 200M */ 101 /* dummy is 200M */
102 cpu: cpu@01c20054 { 102 cpu: cpu@01c20054 {
103 #clock-cells = <0>; 103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-cpu-clk"; 104 compatible = "allwinner,sun4i-a10-cpu-clk";
105 reg = <0x01c20054 0x4>; 105 reg = <0x01c20054 0x4>;
106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; 106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu"; 107 clock-output-names = "cpu";
@@ -109,7 +109,7 @@
109 109
110 axi: axi@01c20054 { 110 axi: axi@01c20054 {
111 #clock-cells = <0>; 111 #clock-cells = <0>;
112 compatible = "allwinner,sun4i-axi-clk"; 112 compatible = "allwinner,sun4i-a10-axi-clk";
113 reg = <0x01c20054 0x4>; 113 reg = <0x01c20054 0x4>;
114 clocks = <&cpu>; 114 clocks = <&cpu>;
115 clock-output-names = "axi"; 115 clock-output-names = "axi";
@@ -117,7 +117,7 @@
117 117
118 axi_gates: clk@01c2005c { 118 axi_gates: clk@01c2005c {
119 #clock-cells = <1>; 119 #clock-cells = <1>;
120 compatible = "allwinner,sun4i-axi-gates-clk"; 120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
121 reg = <0x01c2005c 0x4>; 121 reg = <0x01c2005c 0x4>;
122 clocks = <&axi>; 122 clocks = <&axi>;
123 clock-output-names = "axi_dram"; 123 clock-output-names = "axi_dram";
@@ -125,7 +125,7 @@
125 125
126 ahb: ahb@01c20054 { 126 ahb: ahb@01c20054 {
127 #clock-cells = <0>; 127 #clock-cells = <0>;
128 compatible = "allwinner,sun4i-ahb-clk"; 128 compatible = "allwinner,sun4i-a10-ahb-clk";
129 reg = <0x01c20054 0x4>; 129 reg = <0x01c20054 0x4>;
130 clocks = <&axi>; 130 clocks = <&axi>;
131 clock-output-names = "ahb"; 131 clock-output-names = "ahb";
@@ -147,7 +147,7 @@
147 147
148 apb0: apb0@01c20054 { 148 apb0: apb0@01c20054 {
149 #clock-cells = <0>; 149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-apb0-clk"; 150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>; 151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>; 152 clocks = <&ahb>;
153 clock-output-names = "apb0"; 153 clock-output-names = "apb0";
@@ -164,7 +164,7 @@
164 164
165 apb1_mux: apb1_mux@01c20058 { 165 apb1_mux: apb1_mux@01c20058 {
166 #clock-cells = <0>; 166 #clock-cells = <0>;
167 compatible = "allwinner,sun4i-apb1-mux-clk"; 167 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
168 reg = <0x01c20058 0x4>; 168 reg = <0x01c20058 0x4>;
169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>; 169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1_mux"; 170 clock-output-names = "apb1_mux";
@@ -172,7 +172,7 @@
172 172
173 apb1: apb1@01c20058 { 173 apb1: apb1@01c20058 {
174 #clock-cells = <0>; 174 #clock-cells = <0>;
175 compatible = "allwinner,sun4i-apb1-clk"; 175 compatible = "allwinner,sun4i-a10-apb1-clk";
176 reg = <0x01c20058 0x4>; 176 reg = <0x01c20058 0x4>;
177 clocks = <&apb1_mux>; 177 clocks = <&apb1_mux>;
178 clock-output-names = "apb1"; 178 clock-output-names = "apb1";
@@ -190,7 +190,7 @@
190 190
191 nand_clk: clk@01c20080 { 191 nand_clk: clk@01c20080 {
192 #clock-cells = <0>; 192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-mod0-clk"; 193 compatible = "allwinner,sun4i-a10-mod0-clk";
194 reg = <0x01c20080 0x4>; 194 reg = <0x01c20080 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
196 clock-output-names = "nand"; 196 clock-output-names = "nand";
@@ -198,7 +198,7 @@
198 198
199 ms_clk: clk@01c20084 { 199 ms_clk: clk@01c20084 {
200 #clock-cells = <0>; 200 #clock-cells = <0>;
201 compatible = "allwinner,sun4i-mod0-clk"; 201 compatible = "allwinner,sun4i-a10-mod0-clk";
202 reg = <0x01c20084 0x4>; 202 reg = <0x01c20084 0x4>;
203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
204 clock-output-names = "ms"; 204 clock-output-names = "ms";
@@ -206,7 +206,7 @@
206 206
207 mmc0_clk: clk@01c20088 { 207 mmc0_clk: clk@01c20088 {
208 #clock-cells = <0>; 208 #clock-cells = <0>;
209 compatible = "allwinner,sun4i-mod0-clk"; 209 compatible = "allwinner,sun4i-a10-mod0-clk";
210 reg = <0x01c20088 0x4>; 210 reg = <0x01c20088 0x4>;
211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
212 clock-output-names = "mmc0"; 212 clock-output-names = "mmc0";
@@ -214,7 +214,7 @@
214 214
215 mmc1_clk: clk@01c2008c { 215 mmc1_clk: clk@01c2008c {
216 #clock-cells = <0>; 216 #clock-cells = <0>;
217 compatible = "allwinner,sun4i-mod0-clk"; 217 compatible = "allwinner,sun4i-a10-mod0-clk";
218 reg = <0x01c2008c 0x4>; 218 reg = <0x01c2008c 0x4>;
219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
220 clock-output-names = "mmc1"; 220 clock-output-names = "mmc1";
@@ -222,7 +222,7 @@
222 222
223 mmc2_clk: clk@01c20090 { 223 mmc2_clk: clk@01c20090 {
224 #clock-cells = <0>; 224 #clock-cells = <0>;
225 compatible = "allwinner,sun4i-mod0-clk"; 225 compatible = "allwinner,sun4i-a10-mod0-clk";
226 reg = <0x01c20090 0x4>; 226 reg = <0x01c20090 0x4>;
227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
228 clock-output-names = "mmc2"; 228 clock-output-names = "mmc2";
@@ -230,7 +230,7 @@
230 230
231 ts_clk: clk@01c20098 { 231 ts_clk: clk@01c20098 {
232 #clock-cells = <0>; 232 #clock-cells = <0>;
233 compatible = "allwinner,sun4i-mod0-clk"; 233 compatible = "allwinner,sun4i-a10-mod0-clk";
234 reg = <0x01c20098 0x4>; 234 reg = <0x01c20098 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
236 clock-output-names = "ts"; 236 clock-output-names = "ts";
@@ -238,7 +238,7 @@
238 238
239 ss_clk: clk@01c2009c { 239 ss_clk: clk@01c2009c {
240 #clock-cells = <0>; 240 #clock-cells = <0>;
241 compatible = "allwinner,sun4i-mod0-clk"; 241 compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c2009c 0x4>; 242 reg = <0x01c2009c 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "ss"; 244 clock-output-names = "ss";
@@ -246,7 +246,7 @@
246 246
247 spi0_clk: clk@01c200a0 { 247 spi0_clk: clk@01c200a0 {
248 #clock-cells = <0>; 248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-mod0-clk"; 249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c200a0 0x4>; 250 reg = <0x01c200a0 0x4>;
251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252 clock-output-names = "spi0"; 252 clock-output-names = "spi0";
@@ -254,7 +254,7 @@
254 254
255 spi1_clk: clk@01c200a4 { 255 spi1_clk: clk@01c200a4 {
256 #clock-cells = <0>; 256 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-mod0-clk"; 257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c200a4 0x4>; 258 reg = <0x01c200a4 0x4>;
259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260 clock-output-names = "spi1"; 260 clock-output-names = "spi1";
@@ -262,7 +262,7 @@
262 262
263 spi2_clk: clk@01c200a8 { 263 spi2_clk: clk@01c200a8 {
264 #clock-cells = <0>; 264 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c200a8 0x4>; 266 reg = <0x01c200a8 0x4>;
267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clock-output-names = "spi2"; 268 clock-output-names = "spi2";
@@ -270,7 +270,7 @@
270 270
271 ir0_clk: clk@01c200b0 { 271 ir0_clk: clk@01c200b0 {
272 #clock-cells = <0>; 272 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-mod0-clk"; 273 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c200b0 0x4>; 274 reg = <0x01c200b0 0x4>;
275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
276 clock-output-names = "ir0"; 276 clock-output-names = "ir0";
@@ -287,7 +287,7 @@
287 287
288 mbus_clk: clk@01c2015c { 288 mbus_clk: clk@01c2015c {
289 #clock-cells = <0>; 289 #clock-cells = <0>;
290 compatible = "allwinner,sun4i-mod0-clk"; 290 compatible = "allwinner,sun4i-a10-mod0-clk";
291 reg = <0x01c2015c 0x4>; 291 reg = <0x01c2015c 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "mbus"; 293 clock-output-names = "mbus";
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-06 01:07:32 -0500