diff options
author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-22 16:35:56 -0500 |
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committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-24 04:02:05 -0500 |
commit | 8a689569b13055ca40df4e88f4f3140bd5614825 (patch) | |
tree | 2d61b288c32286ed6e578428d233bfbc5bb8f30d /arch/arm/boot/dts/sun5i-a10s.dtsi | |
parent | 65918e26069a1aa3f693360a0d77bd41cd1b680b (diff) |
ARM: dt: sun5i: Add A10s SPI controller nodes
The A10s has 3 SPI controllers compatible with the one found in the A10. Add
them in the DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun5i-a10s.dtsi')
-rw-r--r-- | arch/arm/boot/dts/sun5i-a10s.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 9cbd88421dbc..503b099a10f5 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi | |||
@@ -300,6 +300,28 @@ | |||
300 | #size-cells = <1>; | 300 | #size-cells = <1>; |
301 | ranges; | 301 | ranges; |
302 | 302 | ||
303 | spi0: spi@01c05000 { | ||
304 | compatible = "allwinner,sun4i-a10-spi"; | ||
305 | reg = <0x01c05000 0x1000>; | ||
306 | interrupts = <10>; | ||
307 | clocks = <&ahb_gates 20>, <&spi0_clk>; | ||
308 | clock-names = "ahb", "mod"; | ||
309 | status = "disabled"; | ||
310 | #address-cells = <1>; | ||
311 | #size-cells = <0>; | ||
312 | }; | ||
313 | |||
314 | spi1: spi@01c06000 { | ||
315 | compatible = "allwinner,sun4i-a10-spi"; | ||
316 | reg = <0x01c06000 0x1000>; | ||
317 | interrupts = <11>; | ||
318 | clocks = <&ahb_gates 21>, <&spi1_clk>; | ||
319 | clock-names = "ahb", "mod"; | ||
320 | status = "disabled"; | ||
321 | #address-cells = <1>; | ||
322 | #size-cells = <0>; | ||
323 | }; | ||
324 | |||
303 | emac: ethernet@01c0b000 { | 325 | emac: ethernet@01c0b000 { |
304 | compatible = "allwinner,sun4i-emac"; | 326 | compatible = "allwinner,sun4i-emac"; |
305 | reg = <0x01c0b000 0x1000>; | 327 | reg = <0x01c0b000 0x1000>; |
@@ -316,6 +338,17 @@ | |||
316 | #size-cells = <0>; | 338 | #size-cells = <0>; |
317 | }; | 339 | }; |
318 | 340 | ||
341 | spi2: spi@01c17000 { | ||
342 | compatible = "allwinner,sun4i-a10-spi"; | ||
343 | reg = <0x01c17000 0x1000>; | ||
344 | interrupts = <12>; | ||
345 | clocks = <&ahb_gates 22>, <&spi2_clk>; | ||
346 | clock-names = "ahb", "mod"; | ||
347 | status = "disabled"; | ||
348 | #address-cells = <1>; | ||
349 | #size-cells = <0>; | ||
350 | }; | ||
351 | |||
319 | intc: interrupt-controller@01c20400 { | 352 | intc: interrupt-controller@01c20400 { |
320 | compatible = "allwinner,sun4i-ic"; | 353 | compatible = "allwinner,sun4i-ic"; |
321 | reg = <0x01c20400 0x400>; | 354 | reg = <0x01c20400 0x400>; |