Merge tag 'sunxi-clk-3.14-for-maxime' of https://bitbucket.org/emiliolopez/linux into sunxi/dt-for-3.14

Allwinner sunXi SoCs DT changes for clocks

This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5
and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks
on most sunxi platforms.

1 files changed, 120 insertions, 2 deletions

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b4764be10a60..50f34fdecdae 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -67,6 +67,29 @@
                         clocks = <&osc24M>;
                 };
 
+                pll4: pll4@01c20018 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20018 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                pll5: pll5@01c20020 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll5-clk";
+                        reg = <0x01c20020 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll5_ddr", "pll5_other";
+                };
+
+                pll6: pll6@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
@@ -127,12 +150,11 @@
                                 "apb0_ir", "apb0_keypad";
                 };
 
-                /* dummy is pll62 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                        clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                 };
 
                 apb1: apb1@01c20058 {
@@ -151,6 +173,102 @@
                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
                                 "apb1_uart2", "apb1_uart3";
                 };
+
+                nand_clk: clk@01c20080 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20080 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "nand";
+                };
+
+                ms_clk: clk@01c20084 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20084 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ms";
+                };
+
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc0";
+                };
+
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc1";
+                };
+
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mmc2";
+                };
+
+                ts_clk: clk@01c20098 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c20098 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ts";
+                };
+
+                ss_clk: clk@01c2009c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2009c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ss";
+                };
+
+                spi0_clk: clk@01c200a0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi0";
+                };
+
+                spi1_clk: clk@01c200a4 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a4 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi1";
+                };
+
+                spi2_clk: clk@01c200a8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200a8 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "spi2";
+                };
+
+                ir0_clk: clk@01c200b0 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c200b0 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "ir0";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-mod0-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                        clock-output-names = "mbus";
+                };
         };
 
         soc@01c00000 {