ARM: STi: DT: STiH41x: Rename CLK_SYSIN into clk_sysin

all-caps node name is not very usual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index a6942c75cbbb..10f8389ce9eb 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -6,16 +6,17 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
 / {
         clocks {
+
                 /*
                  * Fixed 30MHz oscillator inputs to SoC
                  */
-                CLK_SYSIN: CLK_SYSIN {
+                clk_sysin: clk-sysin {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <30000000>;
-                        clock-output-names = "CLK_SYSIN";
                 };
 
                 /*