ARM: ux500: move the HREFv60plus IPGPIO pins to device tree

Move the control of muxing and enabling the IPGPIO (image
processor GPIO) from the static set-up to the device tree.
Use a hog as we have no device for the flash controller yet.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 6e0105d2f461..ecd26848f24f 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -62,6 +62,10 @@
                 };
 
                 pinctrl {
+                        /* Set this up using hogs */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&ipgpio_hrefv60_mode>;
+
                         sdi0 {
                                 /* SD card detect GPIO pin, extend default state */
                                 sdi0_default_mode: sdi0_default {
@@ -71,6 +75,33 @@
                                         };
                                 };
                         };
+                        ipgpio {
+                                /*
+                                 * XENON Flashgun on image processor GPIO (controlled from image
+                                 * processor firmware), mux in these image processor GPIO lines 0
+                                 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
+                                 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
+                                 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
+                                 */
+                                ipgpio_hrefv60_mode: ipgpio_hrefv60 {
+                                        hrefv60_mux {
+                                                ste,function = "ipgpio";
+                                                ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
+                                        };
+                                        hrefv60_cfg1 {
+                                                ste,pins = "GPIO6_AF6", "GPIO7_AG5";
+                                                ste,config = <&in_pu>;
+                                        };
+                                        hrefv60_cfg2 {
+                                                ste,pins = "GPIO21_AB3";
+                                                ste,config = <&gpio_out_lo>;
+                                        };
+                                        hrefv60_cfg3 {
+                                                ste,pins = "GPIO64_F3";
+                                                ste,config = <&out_lo>;
+                                        };
+                                 };
+                        };
                 };
         };
 };