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authorLinus Walleij <linus.walleij@linaro.org>2014-09-30 06:16:25 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-10-20 03:08:26 -0400
commit1637d480f873ca305f7f090e3b3bc92430b5892f (patch)
treec254049d778fe41f11b35623561173873c6a1177 /arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
parent51d39936acba666774b596829277db3e13e5e970 (diff)
pinctrl: nomadik: force-convert to generic config bindings
This converts the Nomadik pin controller and all associated device trees to use the standard, generic config bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-href-family-pinctrl.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-href-family-pinctrl.dtsi150
1 files changed, 75 insertions, 75 deletions
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index 61aa87138927..5c5cea232743 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -22,29 +22,29 @@
22 groups = "u0_a_1"; 22 groups = "u0_a_1";
23 }; 23 };
24 default_cfg1 { 24 default_cfg1 {
25 ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 25 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
26 ste,config = <&in_pu>; 26 ste,config = <&in_pu>;
27 }; 27 };
28 28
29 default_cfg2 { 29 default_cfg2 {
30 ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ 30 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
31 ste,config = <&out_hi>; 31 ste,config = <&out_hi>;
32 }; 32 };
33 }; 33 };
34 34
35 uart0_sleep_mode: uart0_sleep { 35 uart0_sleep_mode: uart0_sleep {
36 sleep_cfg1 { 36 sleep_cfg1 {
37 ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ 37 pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
38 ste,config = <&slpm_in_wkup_pdis>; 38 ste,config = <&slpm_in_wkup_pdis>;
39 }; 39 };
40 40
41 sleep_cfg2 { 41 sleep_cfg2 {
42 ste,pins = "GPIO1_AJ3"; /* RTS */ 42 pins = "GPIO1_AJ3"; /* RTS */
43 ste,config = <&slpm_out_hi_wkup_pdis>; 43 ste,config = <&slpm_out_hi_wkup_pdis>;
44 }; 44 };
45 45
46 sleep_cfg3 { 46 sleep_cfg3 {
47 ste,pins = "GPIO3_AH3"; /* TXD */ 47 pins = "GPIO3_AH3"; /* TXD */
48 ste,config = <&slpm_out_wkup_pdis>; 48 ste,config = <&slpm_out_wkup_pdis>;
49 }; 49 };
50 }; 50 };
@@ -57,24 +57,24 @@
57 groups = "u1rxtx_a_1"; 57 groups = "u1rxtx_a_1";
58 }; 58 };
59 default_cfg1 { 59 default_cfg1 {
60 ste,pins = "GPIO4_AH6"; /* RXD */ 60 pins = "GPIO4_AH6"; /* RXD */
61 ste,config = <&in_pu>; 61 ste,config = <&in_pu>;
62 }; 62 };
63 63
64 default_cfg2 { 64 default_cfg2 {
65 ste,pins = "GPIO5_AG6"; /* TXD */ 65 pins = "GPIO5_AG6"; /* TXD */
66 ste,config = <&out_hi>; 66 ste,config = <&out_hi>;
67 }; 67 };
68 }; 68 };
69 69
70 uart1_sleep_mode: uart1_sleep { 70 uart1_sleep_mode: uart1_sleep {
71 sleep_cfg1 { 71 sleep_cfg1 {
72 ste,pins = "GPIO4_AH6"; /* RXD */ 72 pins = "GPIO4_AH6"; /* RXD */
73 ste,config = <&slpm_in_wkup_pdis>; 73 ste,config = <&slpm_in_wkup_pdis>;
74 }; 74 };
75 75
76 sleep_cfg2 { 76 sleep_cfg2 {
77 ste,pins = "GPIO5_AG6"; /* TXD */ 77 pins = "GPIO5_AG6"; /* TXD */
78 ste,config = <&slpm_out_wkup_pdis>; 78 ste,config = <&slpm_out_wkup_pdis>;
79 }; 79 };
80 }; 80 };
@@ -87,24 +87,24 @@
87 groups = "u2rxtx_c_1"; 87 groups = "u2rxtx_c_1";
88 }; 88 };
89 default_cfg1 { 89 default_cfg1 {
90 ste,pins = "GPIO29_W2"; /* RXD */ 90 pins = "GPIO29_W2"; /* RXD */
91 ste,config = <&in_pu>; 91 ste,config = <&in_pu>;
92 }; 92 };
93 93
94 default_cfg2 { 94 default_cfg2 {
95 ste,pins = "GPIO30_W3"; /* TXD */ 95 pins = "GPIO30_W3"; /* TXD */
96 ste,config = <&out_hi>; 96 ste,config = <&out_hi>;
97 }; 97 };
98 }; 98 };
99 99
100 uart2_sleep_mode: uart2_sleep { 100 uart2_sleep_mode: uart2_sleep {
101 sleep_cfg1 { 101 sleep_cfg1 {
102 ste,pins = "GPIO29_W2"; /* RXD */ 102 pins = "GPIO29_W2"; /* RXD */
103 ste,config = <&in_wkup_pdis>; 103 ste,config = <&in_wkup_pdis>;
104 }; 104 };
105 105
106 sleep_cfg2 { 106 sleep_cfg2 {
107 ste,pins = "GPIO30_W3"; /* TXD */ 107 pins = "GPIO30_W3"; /* TXD */
108 ste,config = <&out_wkup_pdis>; 108 ste,config = <&out_wkup_pdis>;
109 }; 109 };
110 }; 110 };
@@ -118,14 +118,14 @@
118 groups = "i2c0_a_1"; 118 groups = "i2c0_a_1";
119 }; 119 };
120 default_cfg1 { 120 default_cfg1 {
121 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 121 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
122 ste,config = <&in_pu>; 122 ste,config = <&in_pu>;
123 }; 123 };
124 }; 124 };
125 125
126 i2c0_sleep_mode: i2c_sleep { 126 i2c0_sleep_mode: i2c_sleep {
127 sleep_cfg1 { 127 sleep_cfg1 {
128 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ 128 pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
129 ste,config = <&slpm_in_wkup_pdis>; 129 ste,config = <&slpm_in_wkup_pdis>;
130 }; 130 };
131 }; 131 };
@@ -138,14 +138,14 @@
138 groups = "i2c1_b_2"; 138 groups = "i2c1_b_2";
139 }; 139 };
140 default_cfg1 { 140 default_cfg1 {
141 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 141 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
142 ste,config = <&in_pu>; 142 ste,config = <&in_pu>;
143 }; 143 };
144 }; 144 };
145 145
146 i2c1_sleep_mode: i2c_sleep { 146 i2c1_sleep_mode: i2c_sleep {
147 sleep_cfg1 { 147 sleep_cfg1 {
148 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ 148 pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
149 ste,config = <&slpm_in_wkup_pdis>; 149 ste,config = <&slpm_in_wkup_pdis>;
150 }; 150 };
151 }; 151 };
@@ -158,14 +158,14 @@
158 groups = "i2c2_b_2"; 158 groups = "i2c2_b_2";
159 }; 159 };
160 default_cfg1 { 160 default_cfg1 {
161 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 161 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
162 ste,config = <&in_pu>; 162 ste,config = <&in_pu>;
163 }; 163 };
164 }; 164 };
165 165
166 i2c2_sleep_mode: i2c_sleep { 166 i2c2_sleep_mode: i2c_sleep {
167 sleep_cfg1 { 167 sleep_cfg1 {
168 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ 168 pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
169 ste,config = <&slpm_in_wkup_pdis>; 169 ste,config = <&slpm_in_wkup_pdis>;
170 }; 170 };
171 }; 171 };
@@ -178,14 +178,14 @@
178 groups = "i2c3_c_2"; 178 groups = "i2c3_c_2";
179 }; 179 };
180 default_cfg1 { 180 default_cfg1 {
181 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 181 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182 ste,config = <&in_pu>; 182 ste,config = <&in_pu>;
183 }; 183 };
184 }; 184 };
185 185
186 i2c3_sleep_mode: i2c_sleep { 186 i2c3_sleep_mode: i2c_sleep {
187 sleep_cfg1 { 187 sleep_cfg1 {
188 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ 188 pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189 ste,config = <&slpm_in_wkup_pdis>; 189 ste,config = <&slpm_in_wkup_pdis>;
190 }; 190 };
191 }; 191 };
@@ -202,14 +202,14 @@
202 groups = "i2c4_b_1"; 202 groups = "i2c4_b_1";
203 }; 203 };
204 default_cfg1 { 204 default_cfg1 {
205 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 205 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206 ste,config = <&in_pu>; 206 ste,config = <&in_pu>;
207 }; 207 };
208 }; 208 };
209 209
210 i2c4_sleep_mode: i2c_sleep { 210 i2c4_sleep_mode: i2c_sleep {
211 sleep_cfg1 { 211 sleep_cfg1 {
212 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ 212 pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213 ste,config = <&slpm_in_wkup_pdis>; 213 ste,config = <&slpm_in_wkup_pdis>;
214 }; 214 };
215 }; 215 };
@@ -223,15 +223,15 @@
223 groups = "spi2_oc1_2"; 223 groups = "spi2_oc1_2";
224 }; 224 };
225 default_cfg1 { 225 default_cfg1 {
226 ste,pins = "GPIO216_AG12"; /* FRM */ 226 pins = "GPIO216_AG12"; /* FRM */
227 ste,config = <&gpio_out_hi>; 227 ste,config = <&gpio_out_hi>;
228 }; 228 };
229 default_cfg2 { 229 default_cfg2 {
230 ste,pins = "GPIO218_AH11"; /* RXD */ 230 pins = "GPIO218_AH11"; /* RXD */
231 ste,config = <&in_pd>; 231 ste,config = <&in_pd>;
232 }; 232 };
233 default_cfg3 { 233 default_cfg3 {
234 ste,pins = 234 pins =
235 "GPIO215_AH13", /* TXD */ 235 "GPIO215_AH13", /* TXD */
236 "GPIO217_AH12"; /* CLK */ 236 "GPIO217_AH12"; /* CLK */
237 ste,config = <&out_lo>; 237 ste,config = <&out_lo>;
@@ -245,32 +245,32 @@
245 * as we do not state any muxing. 245 * as we do not state any muxing.
246 */ 246 */
247 idle_cfg1 { 247 idle_cfg1 {
248 ste,pins = "GPIO218_AH11"; /* RXD */ 248 pins = "GPIO218_AH11"; /* RXD */
249 ste,config = <&slpm_in_pdis>; 249 ste,config = <&slpm_in_pdis>;
250 }; 250 };
251 idle_cfg2 { 251 idle_cfg2 {
252 ste,pins = "GPIO215_AH13"; /* TXD */ 252 pins = "GPIO215_AH13"; /* TXD */
253 ste,config = <&slpm_out_lo_pdis>; 253 ste,config = <&slpm_out_lo_pdis>;
254 }; 254 };
255 idle_cfg3 { 255 idle_cfg3 {
256 ste,pins = "GPIO217_AH12"; /* CLK */ 256 pins = "GPIO217_AH12"; /* CLK */
257 ste,config = <&slpm_pdis>; 257 ste,config = <&slpm_pdis>;
258 }; 258 };
259 }; 259 };
260 260
261 spi2_sleep_mode: spi_sleep { 261 spi2_sleep_mode: spi_sleep {
262 sleep_cfg1 { 262 sleep_cfg1 {
263 ste,pins = 263 pins =
264 "GPIO216_AG12", /* FRM */ 264 "GPIO216_AG12", /* FRM */
265 "GPIO218_AH11"; /* RXD */ 265 "GPIO218_AH11"; /* RXD */
266 ste,config = <&slpm_in_wkup_pdis>; 266 ste,config = <&slpm_in_wkup_pdis>;
267 }; 267 };
268 sleep_cfg2 { 268 sleep_cfg2 {
269 ste,pins = "GPIO215_AH13"; /* TXD */ 269 pins = "GPIO215_AH13"; /* TXD */
270 ste,config = <&slpm_out_lo_wkup_pdis>; 270 ste,config = <&slpm_out_lo_wkup_pdis>;
271 }; 271 };
272 sleep_cfg3 { 272 sleep_cfg3 {
273 ste,pins = "GPIO217_AH12"; /* CLK */ 273 pins = "GPIO217_AH12"; /* CLK */
274 ste,config = <&slpm_wkup_pdis>; 274 ste,config = <&slpm_wkup_pdis>;
275 }; 275 };
276 }; 276 };
@@ -285,22 +285,22 @@
285 groups = "mc0_a_1"; 285 groups = "mc0_a_1";
286 }; 286 };
287 default_cfg1 { 287 default_cfg1 {
288 ste,pins = 288 pins =
289 "GPIO18_AC2", /* CMDDIR */ 289 "GPIO18_AC2", /* CMDDIR */
290 "GPIO19_AC1", /* DAT0DIR */ 290 "GPIO19_AC1", /* DAT0DIR */
291 "GPIO20_AB4"; /* DAT2DIR */ 291 "GPIO20_AB4"; /* DAT2DIR */
292 ste,config = <&out_hi>; 292 ste,config = <&out_hi>;
293 }; 293 };
294 default_cfg2 { 294 default_cfg2 {
295 ste,pins = "GPIO22_AA3"; /* FBCLK */ 295 pins = "GPIO22_AA3"; /* FBCLK */
296 ste,config = <&in_nopull>; 296 ste,config = <&in_nopull>;
297 }; 297 };
298 default_cfg3 { 298 default_cfg3 {
299 ste,pins = "GPIO23_AA4"; /* CLK */ 299 pins = "GPIO23_AA4"; /* CLK */
300 ste,config = <&out_lo>; 300 ste,config = <&out_lo>;
301 }; 301 };
302 default_cfg4 { 302 default_cfg4 {
303 ste,pins = 303 pins =
304 "GPIO24_AB2", /* CMD */ 304 "GPIO24_AB2", /* CMD */
305 "GPIO25_Y4", /* DAT0 */ 305 "GPIO25_Y4", /* DAT0 */
306 "GPIO26_Y2", /* DAT1 */ 306 "GPIO26_Y2", /* DAT1 */
@@ -312,14 +312,14 @@
312 312
313 sdi0_sleep_mode: sdi0_sleep { 313 sdi0_sleep_mode: sdi0_sleep {
314 sleep_cfg1 { 314 sleep_cfg1 {
315 ste,pins = 315 pins =
316 "GPIO18_AC2", /* CMDDIR */ 316 "GPIO18_AC2", /* CMDDIR */
317 "GPIO19_AC1", /* DAT0DIR */ 317 "GPIO19_AC1", /* DAT0DIR */
318 "GPIO20_AB4"; /* DAT2DIR */ 318 "GPIO20_AB4"; /* DAT2DIR */
319 ste,config = <&slpm_out_hi_wkup_pdis>; 319 ste,config = <&slpm_out_hi_wkup_pdis>;
320 }; 320 };
321 sleep_cfg2 { 321 sleep_cfg2 {
322 ste,pins = 322 pins =
323 "GPIO22_AA3", /* FBCLK */ 323 "GPIO22_AA3", /* FBCLK */
324 "GPIO24_AB2", /* CMD */ 324 "GPIO24_AB2", /* CMD */
325 "GPIO25_Y4", /* DAT0 */ 325 "GPIO25_Y4", /* DAT0 */
@@ -329,7 +329,7 @@
329 ste,config = <&slpm_in_wkup_pdis>; 329 ste,config = <&slpm_in_wkup_pdis>;
330 }; 330 };
331 sleep_cfg3 { 331 sleep_cfg3 {
332 ste,pins = "GPIO23_AA4"; /* CLK */ 332 pins = "GPIO23_AA4"; /* CLK */
333 ste,config = <&slpm_out_lo_wkup_pdis>; 333 ste,config = <&slpm_out_lo_wkup_pdis>;
334 }; 334 };
335 }; 335 };
@@ -343,15 +343,15 @@
343 groups = "mc1_a_1"; 343 groups = "mc1_a_1";
344 }; 344 };
345 default_cfg1 { 345 default_cfg1 {
346 ste,pins = "GPIO208_AH16"; /* CLK */ 346 pins = "GPIO208_AH16"; /* CLK */
347 ste,config = <&out_lo>; 347 ste,config = <&out_lo>;
348 }; 348 };
349 default_cfg2 { 349 default_cfg2 {
350 ste,pins = "GPIO209_AG15"; /* FBCLK */ 350 pins = "GPIO209_AG15"; /* FBCLK */
351 ste,config = <&in_nopull>; 351 ste,config = <&in_nopull>;
352 }; 352 };
353 default_cfg3 { 353 default_cfg3 {
354 ste,pins = 354 pins =
355 "GPIO210_AJ15", /* CMD */ 355 "GPIO210_AJ15", /* CMD */
356 "GPIO211_AG14", /* DAT0 */ 356 "GPIO211_AG14", /* DAT0 */
357 "GPIO212_AF13", /* DAT1 */ 357 "GPIO212_AF13", /* DAT1 */
@@ -363,11 +363,11 @@
363 363
364 sdi1_sleep_mode: sdi1_sleep { 364 sdi1_sleep_mode: sdi1_sleep {
365 sleep_cfg1 { 365 sleep_cfg1 {
366 ste,pins = "GPIO208_AH16"; /* CLK */ 366 pins = "GPIO208_AH16"; /* CLK */
367 ste,config = <&slpm_out_lo_wkup_pdis>; 367 ste,config = <&slpm_out_lo_wkup_pdis>;
368 }; 368 };
369 sleep_cfg2 { 369 sleep_cfg2 {
370 ste,pins = 370 pins =
371 "GPIO209_AG15", /* FBCLK */ 371 "GPIO209_AG15", /* FBCLK */
372 "GPIO210_AJ15", /* CMD */ 372 "GPIO210_AJ15", /* CMD */
373 "GPIO211_AG14", /* DAT0 */ 373 "GPIO211_AG14", /* DAT0 */
@@ -387,15 +387,15 @@
387 groups = "mc2_a_1"; 387 groups = "mc2_a_1";
388 }; 388 };
389 default_cfg1 { 389 default_cfg1 {
390 ste,pins = "GPIO128_A5"; /* CLK */ 390 pins = "GPIO128_A5"; /* CLK */
391 ste,config = <&out_lo>; 391 ste,config = <&out_lo>;
392 }; 392 };
393 default_cfg2 { 393 default_cfg2 {
394 ste,pins = "GPIO130_C8"; /* FBCLK */ 394 pins = "GPIO130_C8"; /* FBCLK */
395 ste,config = <&in_nopull>; 395 ste,config = <&in_nopull>;
396 }; 396 };
397 default_cfg3 { 397 default_cfg3 {
398 ste,pins = 398 pins =
399 "GPIO129_B4", /* CMD */ 399 "GPIO129_B4", /* CMD */
400 "GPIO131_A12", /* DAT0 */ 400 "GPIO131_A12", /* DAT0 */
401 "GPIO132_C10", /* DAT1 */ 401 "GPIO132_C10", /* DAT1 */
@@ -411,17 +411,17 @@
411 411
412 sdi2_sleep_mode: sdi2_sleep { 412 sdi2_sleep_mode: sdi2_sleep {
413 sleep_cfg1 { 413 sleep_cfg1 {
414 ste,pins = "GPIO128_A5"; /* CLK */ 414 pins = "GPIO128_A5"; /* CLK */
415 ste,config = <&out_lo_wkup_pdis>; 415 ste,config = <&out_lo_wkup_pdis>;
416 }; 416 };
417 sleep_cfg2 { 417 sleep_cfg2 {
418 ste,pins = 418 pins =
419 "GPIO130_C8", /* FBCLK */ 419 "GPIO130_C8", /* FBCLK */
420 "GPIO129_B4"; /* CMD */ 420 "GPIO129_B4"; /* CMD */
421 ste,config = <&in_wkup_pdis_en>; 421 ste,config = <&in_wkup_pdis_en>;
422 }; 422 };
423 sleep_cfg3 { 423 sleep_cfg3 {
424 ste,pins = 424 pins =
425 "GPIO131_A12", /* DAT0 */ 425 "GPIO131_A12", /* DAT0 */
426 "GPIO132_C10", /* DAT1 */ 426 "GPIO132_C10", /* DAT1 */
427 "GPIO133_B10", /* DAT2 */ 427 "GPIO133_B10", /* DAT2 */
@@ -443,15 +443,15 @@
443 groups = "mc4_a_1"; 443 groups = "mc4_a_1";
444 }; 444 };
445 default_cfg1 { 445 default_cfg1 {
446 ste,pins = "GPIO203_AE23"; /* CLK */ 446 pins = "GPIO203_AE23"; /* CLK */
447 ste,config = <&out_lo>; 447 ste,config = <&out_lo>;
448 }; 448 };
449 default_cfg2 { 449 default_cfg2 {
450 ste,pins = "GPIO202_AF25"; /* FBCLK */ 450 pins = "GPIO202_AF25"; /* FBCLK */
451 ste,config = <&in_nopull>; 451 ste,config = <&in_nopull>;
452 }; 452 };
453 default_cfg3 { 453 default_cfg3 {
454 ste,pins = 454 pins =
455 "GPIO201_AF24", /* CMD */ 455 "GPIO201_AF24", /* CMD */
456 "GPIO200_AH26", /* DAT0 */ 456 "GPIO200_AH26", /* DAT0 */
457 "GPIO199_AH23", /* DAT1 */ 457 "GPIO199_AH23", /* DAT1 */
@@ -467,11 +467,11 @@
467 467
468 sdi4_sleep_mode: sdi4_sleep { 468 sdi4_sleep_mode: sdi4_sleep {
469 sleep_cfg1 { 469 sleep_cfg1 {
470 ste,pins = "GPIO203_AE23"; /* CLK */ 470 pins = "GPIO203_AE23"; /* CLK */
471 ste,config = <&out_lo_wkup_pdis>; 471 ste,config = <&out_lo_wkup_pdis>;
472 }; 472 };
473 sleep_cfg2 { 473 sleep_cfg2 {
474 ste,pins = 474 pins =
475 "GPIO202_AF25", /* FBCLK */ 475 "GPIO202_AF25", /* FBCLK */
476 "GPIO201_AF24", /* CMD */ 476 "GPIO201_AF24", /* CMD */
477 "GPIO200_AH26", /* DAT0 */ 477 "GPIO200_AH26", /* DAT0 */
@@ -498,7 +498,7 @@
498 groups = "msp0txrx_a_1", "msp0tfstck_a_1"; 498 groups = "msp0txrx_a_1", "msp0tfstck_a_1";
499 }; 499 };
500 default_msp0_cfg { 500 default_msp0_cfg {
501 ste,pins = 501 pins =
502 "GPIO12_AC4", /* TXD */ 502 "GPIO12_AC4", /* TXD */
503 "GPIO15_AC3", /* RXD */ 503 "GPIO15_AC3", /* RXD */
504 "GPIO13_AF3", /* TFS */ 504 "GPIO13_AF3", /* TFS */
@@ -515,11 +515,11 @@
515 groups = "msp1txrx_a_1", "msp1_a_1"; 515 groups = "msp1txrx_a_1", "msp1_a_1";
516 }; 516 };
517 default_cfg1 { 517 default_cfg1 {
518 ste,pins = "GPIO33_AF2"; 518 pins = "GPIO33_AF2";
519 ste,config = <&out_lo>; 519 ste,config = <&out_lo>;
520 }; 520 };
521 default_cfg2 { 521 default_cfg2 {
522 ste,pins = 522 pins =
523 "GPIO34_AE1", 523 "GPIO34_AE1",
524 "GPIO35_AE2", 524 "GPIO35_AE2",
525 "GPIO36_AG2"; 525 "GPIO36_AG2";
@@ -537,14 +537,14 @@
537 groups = "msp2_a_1"; 537 groups = "msp2_a_1";
538 }; 538 };
539 default_cfg1 { 539 default_cfg1 {
540 ste,pins = 540 pins =
541 "GPIO193_AH27", /* TXD */ 541 "GPIO193_AH27", /* TXD */
542 "GPIO194_AF27", /* TCK */ 542 "GPIO194_AF27", /* TCK */
543 "GPIO195_AG28"; /* TFS */ 543 "GPIO195_AG28"; /* TFS */
544 ste,config = <&in_pd>; 544 ste,config = <&in_pd>;
545 }; 545 };
546 default_cfg2 { 546 default_cfg2 {
547 ste,pins = "GPIO196_AG26"; /* RXD */ 547 pins = "GPIO196_AG26"; /* RXD */
548 ste,config = <&out_lo>; 548 ste,config = <&out_lo>;
549 }; 549 };
550 }; 550 };
@@ -558,7 +558,7 @@
558 groups = "usb_a_1"; 558 groups = "usb_a_1";
559 }; 559 };
560 default_cfg1 { 560 default_cfg1 {
561 ste,pins = 561 pins =
562 "GPIO256_AF28", /* NXT */ 562 "GPIO256_AF28", /* NXT */
563 "GPIO258_AD29", /* XCLK */ 563 "GPIO258_AD29", /* XCLK */
564 "GPIO259_AC29", /* DIR */ 564 "GPIO259_AC29", /* DIR */
@@ -573,25 +573,25 @@
573 ste,config = <&in_nopull>; 573 ste,config = <&in_nopull>;
574 }; 574 };
575 default_cfg2 { 575 default_cfg2 {
576 ste,pins = "GPIO257_AE29"; /* STP */ 576 pins = "GPIO257_AE29"; /* STP */
577 ste,config = <&out_hi>; 577 ste,config = <&out_hi>;
578 }; 578 };
579 }; 579 };
580 580
581 musb_sleep_mode: musb_sleep { 581 musb_sleep_mode: musb_sleep {
582 sleep_cfg1 { 582 sleep_cfg1 {
583 ste,pins = 583 pins =
584 "GPIO256_AF28", /* NXT */ 584 "GPIO256_AF28", /* NXT */
585 "GPIO258_AD29", /* XCLK */ 585 "GPIO258_AD29", /* XCLK */
586 "GPIO259_AC29"; /* DIR */ 586 "GPIO259_AC29"; /* DIR */
587 ste,config = <&slpm_wkup_pdis_en>; 587 ste,config = <&slpm_wkup_pdis_en>;
588 }; 588 };
589 sleep_cfg2 { 589 sleep_cfg2 {
590 ste,pins = "GPIO257_AE29"; /* STP */ 590 pins = "GPIO257_AE29"; /* STP */
591 ste,config = <&slpm_out_hi_wkup_pdis>; 591 ste,config = <&slpm_out_hi_wkup_pdis>;
592 }; 592 };
593 sleep_cfg3 { 593 sleep_cfg3 {
594 ste,pins = 594 pins =
595 "GPIO260_AD28", /* DAT7 */ 595 "GPIO260_AD28", /* DAT7 */
596 "GPIO261_AD26", /* DAT6 */ 596 "GPIO261_AD26", /* DAT6 */
597 "GPIO262_AE26", /* DAT5 */ 597 "GPIO262_AE26", /* DAT5 */
@@ -618,7 +618,7 @@
618 "lcdvsi1_a_1"; /* VSI1 for HDMI */ 618 "lcdvsi1_a_1"; /* VSI1 for HDMI */
619 }; 619 };
620 default_cfg1 { 620 default_cfg1 {
621 ste,pins = 621 pins =
622 "GPIO68_E1", /* VSI0 */ 622 "GPIO68_E1", /* VSI0 */
623 "GPIO69_E2"; /* VSI1 */ 623 "GPIO69_E2"; /* VSI1 */
624 ste,config = <&in_pu>; 624 ste,config = <&in_pu>;
@@ -626,7 +626,7 @@
626 }; 626 };
627 lcd_sleep_mode: lcd_sleep { 627 lcd_sleep_mode: lcd_sleep {
628 sleep_cfg1 { 628 sleep_cfg1 {
629 ste,pins = "GPIO69_E2"; /* VSI1 */ 629 pins = "GPIO69_E2"; /* VSI1 */
630 ste,config = <&slpm_in_wkup_pdis>; 630 ste,config = <&slpm_in_wkup_pdis>;
631 }; 631 };
632 }; 632 };
@@ -640,7 +640,7 @@
640 groups = "kp_a_2"; 640 groups = "kp_a_2";
641 }; 641 };
642 default_cfg1 { 642 default_cfg1 {
643 ste,pins = 643 pins =
644 "GPIO153_B17", /* I7 */ 644 "GPIO153_B17", /* I7 */
645 "GPIO154_C16", /* I6 */ 645 "GPIO154_C16", /* I6 */
646 "GPIO155_C19", /* I5 */ 646 "GPIO155_C19", /* I5 */
@@ -652,7 +652,7 @@
652 ste,config = <&in_pd>; 652 ste,config = <&in_pd>;
653 }; 653 };
654 default_cfg2 { 654 default_cfg2 {
655 ste,pins = 655 pins =
656 "GPIO157_A18", /* O7 */ 656 "GPIO157_A18", /* O7 */
657 "GPIO158_C18", /* O6 */ 657 "GPIO158_C18", /* O6 */
658 "GPIO159_B19", /* O5 */ 658 "GPIO159_B19", /* O5 */
@@ -666,7 +666,7 @@
666 }; 666 };
667 ske_kpa2_sleep_mode: ske_kpa2_sleep { 667 ske_kpa2_sleep_mode: ske_kpa2_sleep {
668 sleep_cfg1 { 668 sleep_cfg1 {
669 ste,pins = 669 pins =
670 "GPIO153_B17", /* I7 */ 670 "GPIO153_B17", /* I7 */
671 "GPIO154_C16", /* I6 */ 671 "GPIO154_C16", /* I6 */
672 "GPIO155_C19", /* I5 */ 672 "GPIO155_C19", /* I5 */
@@ -678,7 +678,7 @@
678 ste,config = <&slpm_in_pu_wkup_pdis_en>; 678 ste,config = <&slpm_in_pu_wkup_pdis_en>;
679 }; 679 };
680 sleep_cfg2 { 680 sleep_cfg2 {
681 ste,pins = 681 pins =
682 "GPIO157_A18", /* O7 */ 682 "GPIO157_A18", /* O7 */
683 "GPIO158_C18", /* O6 */ 683 "GPIO158_C18", /* O6 */
684 "GPIO159_B19", /* O5 */ 684 "GPIO159_B19", /* O5 */
@@ -700,7 +700,7 @@
700 groups = "kp_a_1", "kp_oc1_1"; 700 groups = "kp_a_1", "kp_oc1_1";
701 }; 701 };
702 default_cfg1 { 702 default_cfg1 {
703 ste,pins = 703 pins =
704 "GPIO91_B6", /* KP_O0 */ 704 "GPIO91_B6", /* KP_O0 */
705 "GPIO90_A3", /* KP_O1 */ 705 "GPIO90_A3", /* KP_O1 */
706 "GPIO87_B3", /* KP_O2 */ 706 "GPIO87_B3", /* KP_O2 */
@@ -710,7 +710,7 @@
710 ste,config = <&out_lo>; 710 ste,config = <&out_lo>;
711 }; 711 };
712 default_cfg2 { 712 default_cfg2 {
713 ste,pins = 713 pins =
714 "GPIO93_B7", /* KP_I0 */ 714 "GPIO93_B7", /* KP_I0 */
715 "GPIO92_D6", /* KP_I1 */ 715 "GPIO92_D6", /* KP_I1 */
716 "GPIO89_E6", /* KP_I2 */ 716 "GPIO89_E6", /* KP_I2 */
@@ -729,13 +729,13 @@
729 * These are plain GPIO pins used by WLAN 729 * These are plain GPIO pins used by WLAN
730 */ 730 */
731 default_cfg1 { 731 default_cfg1 {
732 ste,pins = 732 pins =
733 "GPIO226_AF8", /* WLAN_PMU_EN */ 733 "GPIO226_AF8", /* WLAN_PMU_EN */
734 "GPIO85_D5"; /* WLAN_ENA */ 734 "GPIO85_D5"; /* WLAN_ENA */
735 ste,config = <&gpio_out_lo>; 735 ste,config = <&gpio_out_lo>;
736 }; 736 };
737 default_cfg2 { 737 default_cfg2 {
738 ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ 738 pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
739 ste,config = <&gpio_in_pu>; 739 ste,config = <&gpio_in_pu>;
740 }; 740 };
741 }; 741 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 20:11:49 -0500