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authorLinus Walleij <linus.walleij@linaro.org>2014-09-30 06:16:25 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-10-20 03:08:26 -0400
commit1637d480f873ca305f7f090e3b3bc92430b5892f (patch)
treec254049d778fe41f11b35623561173873c6a1177 /arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
parent51d39936acba666774b596829277db3e13e5e970 (diff)
pinctrl: nomadik: force-convert to generic config bindings
This converts the Nomadik pin controller and all associated device trees to use the standard, generic config bindings for pin controllers. There are no such device trees deployed in the wild so this is safe to do to set a good example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
index 08a7365cb929..52dba2e39c71 100644
--- a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
@@ -23,24 +23,24 @@
23 23
24 uart0_default_mode: uart0_default { 24 uart0_default_mode: uart0_default {
25 default_cfg1 { 25 default_cfg1 {
26 ste,pins = "GPIO0", "GPIO2"; 26 pins = "GPIO0", "GPIO2";
27 ste,config = <&in_pu>; 27 ste,config = <&in_pu>;
28 }; 28 };
29 29
30 default_cfg2 { 30 default_cfg2 {
31 ste,pins = "GPIO1", "GPIO3"; 31 pins = "GPIO1", "GPIO3";
32 ste,config = <&out_hi>; 32 ste,config = <&out_hi>;
33 }; 33 };
34 }; 34 };
35 35
36 uart0_sleep_mode: uart0_sleep { 36 uart0_sleep_mode: uart0_sleep {
37 sleep_cfg1 { 37 sleep_cfg1 {
38 ste,pins = "GPIO0", "GPIO2"; 38 pins = "GPIO0", "GPIO2";
39 ste,config = <&slpm_in_pu>; 39 ste,config = <&slpm_in_pu>;
40 }; 40 };
41 41
42 sleep_cfg2 { 42 sleep_cfg2 {
43 ste,pins = "GPIO1", "GPIO3"; 43 pins = "GPIO1", "GPIO3";
44 ste,config = <&slpm_out_hi>; 44 ste,config = <&slpm_out_hi>;
45 }; 45 };
46 }; 46 };
@@ -54,24 +54,24 @@
54 }; 54 };
55 55
56 default_cfg1 { 56 default_cfg1 {
57 ste,pins = "GPIO120"; 57 pins = "GPIO120";
58 ste,config = <&in_pu>; 58 ste,config = <&in_pu>;
59 }; 59 };
60 60
61 default_cfg2 { 61 default_cfg2 {
62 ste,pins = "GPIO121"; 62 pins = "GPIO121";
63 ste,config = <&out_hi>; 63 ste,config = <&out_hi>;
64 }; 64 };
65 }; 65 };
66 66
67 uart2_sleep_mode: uart2_sleep { 67 uart2_sleep_mode: uart2_sleep {
68 sleep_cfg1 { 68 sleep_cfg1 {
69 ste,pins = "GPIO120"; 69 pins = "GPIO120";
70 ste,config = <&slpm_in_pu>; 70 ste,config = <&slpm_in_pu>;
71 }; 71 };
72 72
73 sleep_cfg2 { 73 sleep_cfg2 {
74 ste,pins = "GPIO121"; 74 pins = "GPIO121";
75 ste,config = <&slpm_out_hi>; 75 ste,config = <&slpm_out_hi>;
76 }; 76 };
77 }; 77 };
@@ -87,14 +87,14 @@
87 87
88 i2c0_default_mode: i2c_default { 88 i2c0_default_mode: i2c_default {
89 default_cfg1 { 89 default_cfg1 {
90 ste,pins = "GPIO147", "GPIO148"; 90 pins = "GPIO147", "GPIO148";
91 ste,config = <&in_pu>; 91 ste,config = <&in_pu>;
92 }; 92 };
93 }; 93 };
94 94
95 i2c0_sleep_mode: i2c_sleep { 95 i2c0_sleep_mode: i2c_sleep {
96 sleep_cfg1 { 96 sleep_cfg1 {
97 ste,pins = "GPIO147", "GPIO148"; 97 pins = "GPIO147", "GPIO148";
98 ste,config = <&slpm_in_pu>; 98 ste,config = <&slpm_in_pu>;
99 }; 99 };
100 }; 100 };
@@ -110,14 +110,14 @@
110 110
111 i2c1_default_mode: i2c_default { 111 i2c1_default_mode: i2c_default {
112 default_cfg1 { 112 default_cfg1 {
113 ste,pins = "GPIO16", "GPIO17"; 113 pins = "GPIO16", "GPIO17";
114 ste,config = <&in_pu>; 114 ste,config = <&in_pu>;
115 }; 115 };
116 }; 116 };
117 117
118 i2c1_sleep_mode: i2c_sleep { 118 i2c1_sleep_mode: i2c_sleep {
119 sleep_cfg1 { 119 sleep_cfg1 {
120 ste,pins = "GPIO16", "GPIO17"; 120 pins = "GPIO16", "GPIO17";
121 ste,config = <&slpm_in_pu>; 121 ste,config = <&slpm_in_pu>;
122 }; 122 };
123 }; 123 };
@@ -133,14 +133,14 @@
133 133
134 i2c2_default_mode: i2c_default { 134 i2c2_default_mode: i2c_default {
135 default_cfg1 { 135 default_cfg1 {
136 ste,pins = "GPIO10", "GPIO11"; 136 pins = "GPIO10", "GPIO11";
137 ste,config = <&in_pu>; 137 ste,config = <&in_pu>;
138 }; 138 };
139 }; 139 };
140 140
141 i2c2_sleep_mode: i2c_sleep { 141 i2c2_sleep_mode: i2c_sleep {
142 sleep_cfg1 { 142 sleep_cfg1 {
143 ste,pins = "GPIO11", "GPIO11"; 143 pins = "GPIO11", "GPIO11";
144 ste,config = <&slpm_in_pu>; 144 ste,config = <&slpm_in_pu>;
145 }; 145 };
146 }; 146 };
@@ -156,14 +156,14 @@
156 156
157 i2c4_default_mode: i2c_default { 157 i2c4_default_mode: i2c_default {
158 default_cfg1 { 158 default_cfg1 {
159 ste,pins = "GPIO122", "GPIO123"; 159 pins = "GPIO122", "GPIO123";
160 ste,config = <&in_pu>; 160 ste,config = <&in_pu>;
161 }; 161 };
162 }; 162 };
163 163
164 i2c4_sleep_mode: i2c_sleep { 164 i2c4_sleep_mode: i2c_sleep {
165 sleep_cfg1 { 165 sleep_cfg1 {
166 ste,pins = "GPIO122", "GPIO123"; 166 pins = "GPIO122", "GPIO123";
167 ste,config = <&slpm_in_pu>; 167 ste,config = <&slpm_in_pu>;
168 }; 168 };
169 }; 169 };
@@ -179,14 +179,14 @@
179 179
180 i2c5_default_mode: i2c_default { 180 i2c5_default_mode: i2c_default {
181 default_cfg1 { 181 default_cfg1 {
182 ste,pins = "GPIO118", "GPIO119"; 182 pins = "GPIO118", "GPIO119";
183 ste,config = <&in_pu>; 183 ste,config = <&in_pu>;
184 }; 184 };
185 }; 185 };
186 186
187 i2c5_sleep_mode: i2c_sleep { 187 i2c5_sleep_mode: i2c_sleep {
188 sleep_cfg1 { 188 sleep_cfg1 {
189 ste,pins = "GPIO118", "GPIO119"; 189 pins = "GPIO118", "GPIO119";
190 ste,config = <&slpm_in_pu>; 190 ste,config = <&slpm_in_pu>;
191 }; 191 };
192 }; 192 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 06:51:07 -0400