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authorShiraz Hashim <shiraz.hashim@st.com>2012-08-03 06:30:18 -0400
committerViresh Kumar <viresh.kumar@linaro.org>2012-11-26 06:25:32 -0500
commit86edd7b8ac2791ddf42ab082799ddb843813c3bc (patch)
tree4b39c92a300da2be438d7bcfd3ea6ee93e0a1e8d /arch/arm/boot/dts/spear320.dtsi
parent80515a5a2e3c35e2994105f19af27650e8a16c51 (diff)
ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor
shirq layer has been adapted to DT, add corresponding nodes in all SPEAr3xx variants. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/spear320.dtsi')
-rw-r--r--arch/arm/boot/dts/spear320.dtsi24
1 files changed, 22 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index 6ff0d1e0e461..c056a84deabf 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -30,7 +30,8 @@
30 clcd@90000000 { 30 clcd@90000000 {
31 compatible = "arm,pl110", "arm,primecell"; 31 compatible = "arm,pl110", "arm,primecell";
32 reg = <0x90000000 0x1000>; 32 reg = <0x90000000 0x1000>;
33 interrupts = <33>; 33 interrupts = <8>;
34 interrupt-parent = <&shirq>;
34 status = "disabled"; 35 status = "disabled";
35 }; 36 };
36 37
@@ -49,13 +50,24 @@
49 sdhci@70000000 { 50 sdhci@70000000 {
50 compatible = "st,sdhci-spear"; 51 compatible = "st,sdhci-spear";
51 reg = <0x70000000 0x100>; 52 reg = <0x70000000 0x100>;
52 interrupts = <29>; 53 interrupts = <10>;
54 interrupt-parent = <&shirq>;
53 status = "disabled"; 55 status = "disabled";
54 }; 56 };
55 57
58 shirq: interrupt-controller@0xb3000000 {
59 compatible = "st,spear320-shirq";
60 reg = <0xb3000000 0x1000>;
61 interrupts = <30 28 29 1>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 };
65
56 spi1: spi@a5000000 { 66 spi1: spi@a5000000 {
57 compatible = "arm,pl022", "arm,primecell"; 67 compatible = "arm,pl022", "arm,primecell";
58 reg = <0xa5000000 0x1000>; 68 reg = <0xa5000000 0x1000>;
69 interrupts = <15>;
70 interrupt-parent = <&shirq>;
59 #address-cells = <1>; 71 #address-cells = <1>;
60 #size-cells = <0>; 72 #size-cells = <0>;
61 status = "disabled"; 73 status = "disabled";
@@ -64,6 +76,8 @@
64 spi2: spi@a6000000 { 76 spi2: spi@a6000000 {
65 compatible = "arm,pl022", "arm,primecell"; 77 compatible = "arm,pl022", "arm,primecell";
66 reg = <0xa6000000 0x1000>; 78 reg = <0xa6000000 0x1000>;
79 interrupts = <16>;
80 interrupt-parent = <&shirq>;
67 #address-cells = <1>; 81 #address-cells = <1>;
68 #size-cells = <0>; 82 #size-cells = <0>;
69 status = "disabled"; 83 status = "disabled";
@@ -88,18 +102,24 @@
88 #size-cells = <0>; 102 #size-cells = <0>;
89 compatible = "snps,designware-i2c"; 103 compatible = "snps,designware-i2c";
90 reg = <0xa7000000 0x1000>; 104 reg = <0xa7000000 0x1000>;
105 interrupts = <21>;
106 interrupt-parent = <&shirq>;
91 status = "disabled"; 107 status = "disabled";
92 }; 108 };
93 109
94 serial@a3000000 { 110 serial@a3000000 {
95 compatible = "arm,pl011", "arm,primecell"; 111 compatible = "arm,pl011", "arm,primecell";
96 reg = <0xa3000000 0x1000>; 112 reg = <0xa3000000 0x1000>;
113 interrupts = <13>;
114 interrupt-parent = <&shirq>;
97 status = "disabled"; 115 status = "disabled";
98 }; 116 };
99 117
100 serial@a4000000 { 118 serial@a4000000 {
101 compatible = "arm,pl011", "arm,primecell"; 119 compatible = "arm,pl011", "arm,primecell";
102 reg = <0xa4000000 0x1000>; 120 reg = <0xa4000000 0x1000>;
121 interrupts = <14>;
122 interrupt-parent = <&shirq>;
103 status = "disabled"; 123 status = "disabled";
104 }; 124 };
105 125