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authorDinh Nguyen <dinguyen@altera.com>2014-04-02 22:14:57 -0400
committerDinh Nguyen <dinguyen@altera.com>2014-05-05 23:33:15 -0400
commitbd785efda77c073e8ed5c7f29c7bdab6a3f3f6ad (patch)
tree0fe222c0fd1e58e2f656d630b6ce77451234a5c2 /arch/arm/boot/dts/socfpga_cyclone5.dtsi
parent58303f1f961d6a1abc0496790c9c557d67e9ae64 (diff)
ARM: socfpga: dts: Remove hard coded clock-frequency property
The timers and uart can get their clock frequencies using the common clock driver. Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_cyclone5.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi24
1 files changed, 0 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 63a951366a98..bf511828729f 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -45,30 +45,6 @@
45 status = "okay"; 45 status = "okay";
46 }; 46 };
47 47
48 timer0@ffc08000 {
49 clock-frequency = <100000000>;
50 };
51
52 timer1@ffc09000 {
53 clock-frequency = <100000000>;
54 };
55
56 timer2@ffd00000 {
57 clock-frequency = <25000000>;
58 };
59
60 timer3@ffd01000 {
61 clock-frequency = <25000000>;
62 };
63
64 serial0@ffc02000 {
65 clock-frequency = <100000000>;
66 };
67
68 serial1@ffc03000 {
69 clock-frequency = <100000000>;
70 };
71
72 sysmgr@ffd08000 { 48 sysmgr@ffd08000 {
73 cpu1-start-addr = <0xffd080c4>; 49 cpu1-start-addr = <0xffd080c4>;
74 }; 50 };