ARM: socfpga: initial support for Altera's SOCFPGA platform

Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 147 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644
index 000000000000..0772f5739f59
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &gmac0;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        intc: intc@fffed000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xfffed000 0x1000>,
+                      <0xfffec100 0x100>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                device_type = "soc";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        pdma: pdma@ffe01000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xffe01000 0x1000>;
+                                interrupts = <0 180 4>;
+                        };
+                };
+
+                gmac0: stmmac@ff700000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0xff700000 0x2000>;
+                        interrupts = <0 115 4>;
+                        interrupt-names = "macirq";
+                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                        phy-mode = "gmii";
+                };
+
+                L2: l2-cache@fffef000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfffef000 0x1000>;
+                        interrupts = <0 38 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                /* Local timer */
+                timer@fffec600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xfffec600 0x100>;
+                        interrupts = <1 13 0xf04>;
+                };
+
+                timer0: timer@ffc08000 {
+                        compatible = "snps,dw-apb-timer-sp";
+                        interrupts = <0 167 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffc08000 0x1000>;
+                };
+
+                timer1: timer@ffc09000 {
+                        compatible = "snps,dw-apb-timer-sp";
+                        interrupts = <0 168 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffc09000 0x1000>;
+                };
+
+                timer2: timer@ffd00000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        interrupts = <0 169 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffd00000 0x1000>;
+                };
+
+                timer3: timer@ffd01000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        interrupts = <0 170 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffd01000 0x1000>;
+                };
+
+                uart0: uart@ffc02000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02000 0x1000>;
+                        clock-frequency = <7372800>;
+                        interrupts = <0 162 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uart1: uart@ffc03000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc03000 0x1000>;
+                        clock-frequency = <7372800>;
+                        interrupts = <0 163 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+        };
+};