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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2013-04-23 20:34:25 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2013-05-17 06:11:39 -0400
commitc9d0f317c6dc45f84888bc11947bc10e6c547dc3 (patch)
treeef4d865a48a66b378917b101c85eb011f5ca624b /arch/arm/boot/dts/sama5d3.dtsi
parent0e4686e6e662205b87e64af7c0ba9ef81e2c8791 (diff)
ARM: at91: dt: switch to pinctrl to pre-processor
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/sama5d3.dtsi')
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi448
1 files changed, 224 insertions, 224 deletions
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 0d65e3d375a3..05a3380e2b47 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -9,6 +9,7 @@
9 */ 9 */
10 10
11#include "skeleton.dtsi" 11#include "skeleton.dtsi"
12#include <dt-bindings/pinctrl/at91.h>
12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
13 14
14/ { 15/ {
@@ -414,202 +415,202 @@
414 adc0 { 415 adc0 {
415 pinctrl_adc0_adtrg: adc0_adtrg { 416 pinctrl_adc0_adtrg: adc0_adtrg {
416 atmel,pins = 417 atmel,pins =
417 <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ 418 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
418 }; 419 };
419 pinctrl_adc0_ad0: adc0_ad0 { 420 pinctrl_adc0_ad0: adc0_ad0 {
420 atmel,pins = 421 atmel,pins =
421 <3 20 0x1 0x0>; /* PD20 periph A AD0 */ 422 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
422 }; 423 };
423 pinctrl_adc0_ad1: adc0_ad1 { 424 pinctrl_adc0_ad1: adc0_ad1 {
424 atmel,pins = 425 atmel,pins =
425 <3 21 0x1 0x0>; /* PD21 periph A AD1 */ 426 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
426 }; 427 };
427 pinctrl_adc0_ad2: adc0_ad2 { 428 pinctrl_adc0_ad2: adc0_ad2 {
428 atmel,pins = 429 atmel,pins =
429 <3 22 0x1 0x0>; /* PD22 periph A AD2 */ 430 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
430 }; 431 };
431 pinctrl_adc0_ad3: adc0_ad3 { 432 pinctrl_adc0_ad3: adc0_ad3 {
432 atmel,pins = 433 atmel,pins =
433 <3 23 0x1 0x0>; /* PD23 periph A AD3 */ 434 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
434 }; 435 };
435 pinctrl_adc0_ad4: adc0_ad4 { 436 pinctrl_adc0_ad4: adc0_ad4 {
436 atmel,pins = 437 atmel,pins =
437 <3 24 0x1 0x0>; /* PD24 periph A AD4 */ 438 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
438 }; 439 };
439 pinctrl_adc0_ad5: adc0_ad5 { 440 pinctrl_adc0_ad5: adc0_ad5 {
440 atmel,pins = 441 atmel,pins =
441 <3 25 0x1 0x0>; /* PD25 periph A AD5 */ 442 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
442 }; 443 };
443 pinctrl_adc0_ad6: adc0_ad6 { 444 pinctrl_adc0_ad6: adc0_ad6 {
444 atmel,pins = 445 atmel,pins =
445 <3 26 0x1 0x0>; /* PD26 periph A AD6 */ 446 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
446 }; 447 };
447 pinctrl_adc0_ad7: adc0_ad7 { 448 pinctrl_adc0_ad7: adc0_ad7 {
448 atmel,pins = 449 atmel,pins =
449 <3 27 0x1 0x0>; /* PD27 periph A AD7 */ 450 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
450 }; 451 };
451 pinctrl_adc0_ad8: adc0_ad8 { 452 pinctrl_adc0_ad8: adc0_ad8 {
452 atmel,pins = 453 atmel,pins =
453 <3 28 0x1 0x0>; /* PD28 periph A AD8 */ 454 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
454 }; 455 };
455 pinctrl_adc0_ad9: adc0_ad9 { 456 pinctrl_adc0_ad9: adc0_ad9 {
456 atmel,pins = 457 atmel,pins =
457 <3 29 0x1 0x0>; /* PD29 periph A AD9 */ 458 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
458 }; 459 };
459 pinctrl_adc0_ad10: adc0_ad10 { 460 pinctrl_adc0_ad10: adc0_ad10 {
460 atmel,pins = 461 atmel,pins =
461 <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ 462 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
462 }; 463 };
463 pinctrl_adc0_ad11: adc0_ad11 { 464 pinctrl_adc0_ad11: adc0_ad11 {
464 atmel,pins = 465 atmel,pins =
465 <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ 466 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
466 }; 467 };
467 }; 468 };
468 469
469 can0 { 470 can0 {
470 pinctrl_can0_rx_tx: can0_rx_tx { 471 pinctrl_can0_rx_tx: can0_rx_tx {
471 atmel,pins = 472 atmel,pins =
472 <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ 473 <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
473 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ 474 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
474 }; 475 };
475 }; 476 };
476 477
477 can1 { 478 can1 {
478 pinctrl_can1_rx_tx: can1_rx_tx { 479 pinctrl_can1_rx_tx: can1_rx_tx {
479 atmel,pins = 480 atmel,pins =
480 <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ 481 <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
481 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ 482 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
482 }; 483 };
483 }; 484 };
484 485
485 dbgu { 486 dbgu {
486 pinctrl_dbgu: dbgu-0 { 487 pinctrl_dbgu: dbgu-0 {
487 atmel,pins = 488 atmel,pins =
488 <1 30 0x1 0x0 /* PB30 periph A */ 489 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
489 1 31 0x1 0x1>; /* PB31 periph A with pullup */ 490 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
490 }; 491 };
491 }; 492 };
492 493
493 i2c0 { 494 i2c0 {
494 pinctrl_i2c0: i2c0-0 { 495 pinctrl_i2c0: i2c0-0 {
495 atmel,pins = 496 atmel,pins =
496 <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ 497 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
497 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ 498 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
498 }; 499 };
499 }; 500 };
500 501
501 i2c1 { 502 i2c1 {
502 pinctrl_i2c1: i2c1-0 { 503 pinctrl_i2c1: i2c1-0 {
503 atmel,pins = 504 atmel,pins =
504 <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ 505 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
505 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ 506 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
506 }; 507 };
507 }; 508 };
508 509
509 isi { 510 isi {
510 pinctrl_isi: isi-0 { 511 pinctrl_isi: isi-0 {
511 atmel,pins = 512 atmel,pins =
512 <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ 513 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
513 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ 514 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
514 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ 515 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
515 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ 516 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
516 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ 517 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
517 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ 518 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
518 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ 519 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
519 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ 520 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
520 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ 521 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
521 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ 522 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
522 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ 523 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
523 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ 524 AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
524 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ 525 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
525 }; 526 };
526 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { 527 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
527 atmel,pins = 528 atmel,pins =
528 <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ 529 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
529 }; 530 };
530 }; 531 };
531 532
532 lcd { 533 lcd {
533 pinctrl_lcd: lcd-0 { 534 pinctrl_lcd: lcd-0 {
534 atmel,pins = 535 atmel,pins =
535 <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ 536 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA24 periph A LCDPWM */
536 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ 537 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA26 periph A LCDVSYNC */
537 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ 538 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA27 periph A LCDHSYNC */
538 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ 539 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA25 periph A LCDDISP */
539 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ 540 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA29 periph A LCDDEN */
540 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ 541 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA28 periph A LCDPCK */
541 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ 542 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A LCDD0 pin */
542 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ 543 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A LCDD1 pin */
543 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ 544 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA2 periph A LCDD2 pin */
544 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ 545 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA3 periph A LCDD3 pin */
545 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ 546 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA4 periph A LCDD4 pin */
546 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ 547 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA5 periph A LCDD5 pin */
547 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ 548 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA6 periph A LCDD6 pin */
548 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ 549 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A LCDD7 pin */
549 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ 550 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A LCDD8 pin */
550 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ 551 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A LCDD9 pin */
551 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ 552 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A LCDD10 pin */
552 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ 553 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A LCDD11 pin */
553 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ 554 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A LCDD12 pin */
554 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ 555 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A LCDD13 pin */
555 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ 556 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A LCDD14 pin */
556 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ 557 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A LCDD15 pin */
557 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ 558 AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC14 periph C LCDD16 pin */
558 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ 559 AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC13 periph C LCDD17 pin */
559 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ 560 AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC12 periph C LCDD18 pin */
560 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ 561 AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC11 periph C LCDD19 pin */
561 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ 562 AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC10 periph C LCDD20 pin */
562 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ 563 AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC15 periph C LCDD21 pin */
563 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ 564 AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PE27 periph C LCDD22 pin */
564 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ 565 AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
565 }; 566 };
566 }; 567 };
567 568
568 macb0 { 569 macb0 {
569 pinctrl_macb0_data_rgmii: macb0_data_rgmii { 570 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
570 atmel,pins = 571 atmel,pins =
571 <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ 572 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A GTX0, conflicts with PWMH0 */
572 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ 573 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A GTX1, conflicts with PWML0 */
573 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ 574 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A GTX2, conflicts with TK1 */
574 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ 575 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A GTX3, conflicts with TF1 */
575 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ 576 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A GRX0, conflicts with PWMH1 */
576 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ 577 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A GRX1, conflicts with PWML1 */
577 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ 578 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A GRX2, conflicts with TD1 */
578 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ 579 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A GRX3, conflicts with RK1 */
579 }; 580 };
580 pinctrl_macb0_data_gmii: macb0_data_gmii { 581 pinctrl_macb0_data_gmii: macb0_data_gmii {
581 atmel,pins = 582 atmel,pins =
582 <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ 583 <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB19 periph B GTX4, conflicts with MCI1_CDA */
583 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ 584 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
584 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ 585 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
585 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ 586 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
586 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ 587 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
587 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ 588 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB24 periph B GRX5, conflicts with MCI1_CK */
588 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ 589 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB25 periph B GRX6, conflicts with SCK1 */
589 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ 590 AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
590 }; 591 };
591 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { 592 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
592 atmel,pins = 593 atmel,pins =
593 <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ 594 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A GTXCK, conflicts with PWMH2 */
594 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ 595 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
595 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ 596 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
596 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ 597 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
597 1 16 0x1 0x0 /* PB16 periph A GMDC */ 598 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
598 1 17 0x1 0x0 /* PB17 periph A GMDIO */ 599 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
599 1 18 0x1 0x0>; /* PB18 periph A G125CK */ 600 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
600 }; 601 };
601 pinctrl_macb0_signal_gmii: macb0_signal_gmii { 602 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
602 atmel,pins = 603 atmel,pins =
603 <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ 604 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A GTXEN, conflicts with PWML2 */
604 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ 605 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A GTXER, conflicts with RF1 */
605 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ 606 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
606 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ 607 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A GRXDV, conflicts with PWMH3 */
607 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ 608 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A GRXER, conflicts with PWML3 */
608 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ 609 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A GCRS, conflicts with CANRX1 */
609 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ 610 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A GCOL, conflicts with CANTX1 */
610 1 16 0x1 0x0 /* PB16 periph A GMDC */ 611 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A GMDC */
611 1 17 0x1 0x0 /* PB17 periph A GMDIO */ 612 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A GMDIO */
612 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ 613 AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
613 }; 614 };
614 615
615 }; 616 };
@@ -617,252 +618,251 @@
617 macb1 { 618 macb1 {
618 pinctrl_macb1_rmii: macb1_rmii-0 { 619 pinctrl_macb1_rmii: macb1_rmii-0 {
619 atmel,pins = 620 atmel,pins =
620 <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ 621 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC0 periph A ETX0, conflicts with TIOA3 */
621 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ 622 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A ETX1, conflicts with TIOB3 */
622 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ 623 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A ERX0, conflicts with TCLK3 */
623 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ 624 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A ERX1, conflicts with TIOA4 */
624 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ 625 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC4 periph A ETXEN, conflicts with TIOB4 */
625 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ 626 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 periph A ECRSDV,conflicts with TCLK4 */
626 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ 627 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A ERXER, conflicts with TIOA5 */
627 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ 628 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A EREFCK, conflicts with TIOB5 */
628 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ 629 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with TCLK5 */
629 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ 630 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC9 periph A EMDIO */
630 }; 631 };
631 }; 632 };
632 633
633 mmc0 { 634 mmc0 {
634 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 635 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
635 atmel,pins = 636 atmel,pins =
636 <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ 637 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
637 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ 638 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
638 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ 639 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
639 }; 640 };
640 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 641 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
641 atmel,pins = 642 atmel,pins =
642 <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ 643 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
643 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ 644 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
644 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ 645 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
645 }; 646 };
646 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 647 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
647 atmel,pins = 648 atmel,pins =
648 <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ 649 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
649 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ 650 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
650 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ 651 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
651 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ 652 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
652 }; 653 };
653 }; 654 };
654 655
655 mmc1 { 656 mmc1 {
656 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 657 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
657 atmel,pins = 658 atmel,pins =
658 <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ 659 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
659 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ 660 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
660 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ 661 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
661 }; 662 };
662 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 663 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
663 atmel,pins = 664 atmel,pins =
664 <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ 665 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
665 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ 666 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
666 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ 667 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
667 }; 668 };
668 }; 669 };
669 670
670 mmc2 { 671 mmc2 {
671 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { 672 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
672 atmel,pins = 673 atmel,pins =
673 <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ 674 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
674 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ 675 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
675 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ 676 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
676 }; 677 };
677 pinctrl_mmc2_dat1_3: mmc2_dat1_3 { 678 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
678 atmel,pins = 679 atmel,pins =
679 <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ 680 <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
680 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ 681 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
681 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ 682 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
682 }; 683 };
683 }; 684 };
684 685
685 nand0 { 686 nand0 {
686 pinctrl_nand0_ale_cle: nand0_ale_cle-0 { 687 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
687 atmel,pins = 688 atmel,pins =
688 <4 21 0x1 0x1 /* PE21 periph A with pullup */ 689 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
689 4 22 0x1 0x1>; /* PE22 periph A with pullup */ 690 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
690 }; 691 };
691 }; 692 };
692 693
693 pioA: gpio@fffff200 {
694 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
695 reg = <0xfffff200 0x100>;
696 interrupts = <6 4 1>;
697 #gpio-cells = <2>;
698 gpio-controller;
699 interrupt-controller;
700 #interrupt-cells = <2>;
701 };
702
703 pioB: gpio@fffff400 {
704 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
705 reg = <0xfffff400 0x100>;
706 interrupts = <7 4 1>;
707 #gpio-cells = <2>;
708 gpio-controller;
709 interrupt-controller;
710 #interrupt-cells = <2>;
711 };
712
713 pioC: gpio@fffff600 {
714 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
715 reg = <0xfffff600 0x100>;
716 interrupts = <8 4 1>;
717 #gpio-cells = <2>;
718 gpio-controller;
719 interrupt-controller;
720 #interrupt-cells = <2>;
721 };
722
723 pioD: gpio@fffff800 {
724 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
725 reg = <0xfffff800 0x100>;
726 interrupts = <9 4 1>;
727 #gpio-cells = <2>;
728 gpio-controller;
729 interrupt-controller;
730 #interrupt-cells = <2>;
731 };
732
733 pioE: gpio@fffffa00 {
734 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
735 reg = <0xfffffa00 0x100>;
736 interrupts = <10 4 1>;
737 #gpio-cells = <2>;
738 gpio-controller;
739 interrupt-controller;
740 #interrupt-cells = <2>;
741 };
742
743 spi0 { 694 spi0 {
744 pinctrl_spi0: spi0-0 { 695 pinctrl_spi0: spi0-0 {
745 atmel,pins = 696 atmel,pins =
746 <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ 697 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
747 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ 698 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
748 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ 699 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
749 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
750 }; 700 };
751 }; 701 };
752 702
753 spi1 { 703 spi1 {
754 pinctrl_spi1: spi1-0 { 704 pinctrl_spi1: spi1-0 {
755 atmel,pins = 705 atmel,pins =
756 <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ 706 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
757 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ 707 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
758 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ 708 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
759 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
760 }; 709 };
761 }; 710 };
762 711
763 ssc0 { 712 ssc0 {
764 pinctrl_ssc0_tx: ssc0_tx { 713 pinctrl_ssc0_tx: ssc0_tx {
765 atmel,pins = 714 atmel,pins =
766 <2 16 0x1 0x0 /* PC16 periph A TK0 */ 715 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
767 2 17 0x1 0x0 /* PC17 periph A TF0 */ 716 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
768 2 18 0x1 0x0>; /* PC18 periph A TD0 */ 717 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
769 }; 718 };
770 719
771 pinctrl_ssc0_rx: ssc0_rx { 720 pinctrl_ssc0_rx: ssc0_rx {
772 atmel,pins = 721 atmel,pins =
773 <2 19 0x1 0x0 /* PC19 periph A RK0 */ 722 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
774 2 20 0x1 0x0 /* PC20 periph A RF0 */ 723 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
775 2 21 0x1 0x0>; /* PC21 periph A RD0 */ 724 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
776 }; 725 };
777 }; 726 };
778 727
779 ssc1 { 728 ssc1 {
780 pinctrl_ssc1_tx: ssc1_tx { 729 pinctrl_ssc1_tx: ssc1_tx {
781 atmel,pins = 730 atmel,pins =
782 <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ 731 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
783 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ 732 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
784 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ 733 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
785 }; 734 };
786 735
787 pinctrl_ssc1_rx: ssc1_rx { 736 pinctrl_ssc1_rx: ssc1_rx {
788 atmel,pins = 737 atmel,pins =
789 <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ 738 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
790 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ 739 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
791 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ 740 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
792 }; 741 };
793 }; 742 };
794 743
795 uart0 { 744 uart0 {
796 pinctrl_uart0: uart0-0 { 745 pinctrl_uart0: uart0-0 {
797 atmel,pins = 746 atmel,pins =
798 <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ 747 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
799 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ 748 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
800 }; 749 };
801 }; 750 };
802 751
803 uart1 { 752 uart1 {
804 pinctrl_uart1: uart1-0 { 753 pinctrl_uart1: uart1-0 {
805 atmel,pins = 754 atmel,pins =
806 <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ 755 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
807 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ 756 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
808 }; 757 };
809 }; 758 };
810 759
811 usart0 { 760 usart0 {
812 pinctrl_usart0: usart0-0 { 761 pinctrl_usart0: usart0-0 {
813 atmel,pins = 762 atmel,pins =
814 <3 17 0x1 0x0 /* PD17 periph A */ 763 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
815 3 18 0x1 0x1>; /* PD18 periph A with pullup */ 764 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
816 }; 765 };
817 766
818 pinctrl_usart0_rts_cts: usart0_rts_cts-0 { 767 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
819 atmel,pins = 768 atmel,pins =
820 <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ 769 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
821 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ 770 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
822 }; 771 };
823 }; 772 };
824 773
825 usart1 { 774 usart1 {
826 pinctrl_usart1: usart1-0 { 775 pinctrl_usart1: usart1-0 {
827 atmel,pins = 776 atmel,pins =
828 <1 28 0x1 0x0 /* PB28 periph A */ 777 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
829 1 29 0x1 0x1>; /* PB29 periph A with pullup */ 778 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
830 }; 779 };
831 780
832 pinctrl_usart1_rts_cts: usart1_rts_cts-0 { 781 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
833 atmel,pins = 782 atmel,pins =
834 <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ 783 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
835 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ 784 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
836 }; 785 };
837 }; 786 };
838 787
839 usart2 { 788 usart2 {
840 pinctrl_usart2: usart2-0 { 789 pinctrl_usart2: usart2-0 {
841 atmel,pins = 790 atmel,pins =
842 <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ 791 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
843 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ 792 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
844 }; 793 };
845 794
846 pinctrl_usart2_rts_cts: usart2_rts_cts-0 { 795 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
847 atmel,pins = 796 atmel,pins =
848 <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ 797 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
849 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ 798 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
850 }; 799 };
851 }; 800 };
852 801
853 usart3 { 802 usart3 {
854 pinctrl_usart3: usart3-0 { 803 pinctrl_usart3: usart3-0 {
855 atmel,pins = 804 atmel,pins =
856 <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ 805 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
857 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ 806 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
858 }; 807 };
859 808
860 pinctrl_usart3_rts_cts: usart3_rts_cts-0 { 809 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
861 atmel,pins = 810 atmel,pins =
862 <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ 811 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
863 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ 812 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
864 }; 813 };
865 }; 814 };
815
816
817 pioA: gpio@fffff200 {
818 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
819 reg = <0xfffff200 0x100>;
820 interrupts = <6 4 1>;
821 #gpio-cells = <2>;
822 gpio-controller;
823 interrupt-controller;
824 #interrupt-cells = <2>;
825 };
826
827 pioB: gpio@fffff400 {
828 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
829 reg = <0xfffff400 0x100>;
830 interrupts = <7 4 1>;
831 #gpio-cells = <2>;
832 gpio-controller;
833 interrupt-controller;
834 #interrupt-cells = <2>;
835 };
836
837 pioC: gpio@fffff600 {
838 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
839 reg = <0xfffff600 0x100>;
840 interrupts = <8 4 1>;
841 #gpio-cells = <2>;
842 gpio-controller;
843 interrupt-controller;
844 #interrupt-cells = <2>;
845 };
846
847 pioD: gpio@fffff800 {
848 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
849 reg = <0xfffff800 0x100>;
850 interrupts = <9 4 1>;
851 #gpio-cells = <2>;
852 gpio-controller;
853 interrupt-controller;
854 #interrupt-cells = <2>;
855 };
856
857 pioE: gpio@fffffa00 {
858 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
859 reg = <0xfffffa00 0x100>;
860 interrupts = <10 4 1>;
861 #gpio-cells = <2>;
862 gpio-controller;
863 interrupt-controller;
864 #interrupt-cells = <2>;
865 };
866 }; 866 };
867 867
868 pmc: pmc@fffffc00 { 868 pmc: pmc@fffffc00 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 11:57:22 -0500