aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/rk3188.dtsi
diff options
context:
space:
mode:
authorHeiko Stuebner <heiko@sntech.de>2014-07-26 12:44:35 -0400
committerHeiko Stuebner <heiko@sntech.de>2014-07-26 17:19:06 -0400
commitc3030d30d9c99c057b5ddfa289cffa637a2775f5 (patch)
tree2d221f06754ccb8f400ca7c1259d4fbb547722cf /arch/arm/boot/dts/rk3188.dtsi
parentd356d96f8558d69d4b0d4c72d95002e9b6533531 (diff)
ARM: dts: rockchip: remove soc subnodes
Comments received from the rk3288 submission indicated that a generic subnode to group soc components should not be used. So to keep all rockchip devicetree files similar, remove it from rk3066 and rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3188.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi334
1 files changed, 166 insertions, 168 deletions
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 0db541c4e7b3..038d9d45264c 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -52,223 +52,221 @@
52 }; 52 };
53 }; 53 };
54 54
55 soc { 55 global-timer@1013c200 {
56 global-timer@1013c200 { 56 interrupts = <GIC_PPI 11 0xf04>;
57 interrupts = <GIC_PPI 11 0xf04>; 57 };
58
59 local-timer@1013c600 {
60 interrupts = <GIC_PPI 13 0xf04>;
61 };
62
63 sram: sram@10080000 {
64 compatible = "mmio-sram";
65 reg = <0x10080000 0x8000>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges = <0 0x10080000 0x8000>;
69
70 smp-sram@0 {
71 compatible = "rockchip,rk3066-smp-sram";
72 reg = <0x0 0x50>;
58 }; 73 };
74 };
75
76 cru: clock-controller@20000000 {
77 compatible = "rockchip,rk3188-cru";
78 reg = <0x20000000 0x1000>;
79 rockchip,grf = <&grf>;
80
81 #clock-cells = <1>;
82 #reset-cells = <1>;
83 };
59 84
60 local-timer@1013c600 { 85 pinctrl@20008000 {
61 interrupts = <GIC_PPI 13 0xf04>; 86 compatible = "rockchip,rk3188-pinctrl";
87 rockchip,grf = <&grf>;
88 rockchip,pmu = <&pmu>;
89
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 gpio0: gpio0@0x2000a000 {
95 compatible = "rockchip,rk3188-gpio-bank0";
96 reg = <0x2000a000 0x100>;
97 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&cru PCLK_GPIO0>;
99
100 gpio-controller;
101 #gpio-cells = <2>;
102
103 interrupt-controller;
104 #interrupt-cells = <2>;
62 }; 105 };
63 106
64 sram: sram@10080000 { 107 gpio1: gpio1@0x2003c000 {
65 compatible = "mmio-sram"; 108 compatible = "rockchip,gpio-bank";
66 reg = <0x10080000 0x8000>; 109 reg = <0x2003c000 0x100>;
67 #address-cells = <1>; 110 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
68 #size-cells = <1>; 111 clocks = <&cru PCLK_GPIO1>;
69 ranges = <0 0x10080000 0x8000>;
70 112
71 smp-sram@0 { 113 gpio-controller;
72 compatible = "rockchip,rk3066-smp-sram"; 114 #gpio-cells = <2>;
73 reg = <0x0 0x50>; 115
74 }; 116 interrupt-controller;
117 #interrupt-cells = <2>;
75 }; 118 };
76 119
77 cru: clock-controller@20000000 { 120 gpio2: gpio2@2003e000 {
78 compatible = "rockchip,rk3188-cru"; 121 compatible = "rockchip,gpio-bank";
79 reg = <0x20000000 0x1000>; 122 reg = <0x2003e000 0x100>;
80 rockchip,grf = <&grf>; 123 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cru PCLK_GPIO2>;
125
126 gpio-controller;
127 #gpio-cells = <2>;
81 128
82 #clock-cells = <1>; 129 interrupt-controller;
83 #reset-cells = <1>; 130 #interrupt-cells = <2>;
84 }; 131 };
85 132
86 pinctrl@20008000 { 133 gpio3: gpio3@20080000 {
87 compatible = "rockchip,rk3188-pinctrl"; 134 compatible = "rockchip,gpio-bank";
88 rockchip,grf = <&grf>; 135 reg = <0x20080000 0x100>;
89 rockchip,pmu = <&pmu>; 136 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&cru PCLK_GPIO3>;
90 138
91 #address-cells = <1>; 139 gpio-controller;
92 #size-cells = <1>; 140 #gpio-cells = <2>;
93 ranges;
94 141
95 gpio0: gpio0@0x2000a000 { 142 interrupt-controller;
96 compatible = "rockchip,rk3188-gpio-bank0"; 143 #interrupt-cells = <2>;
97 reg = <0x2000a000 0x100>; 144 };
98 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&cru PCLK_GPIO0>;
100 145
101 gpio-controller; 146 pcfg_pull_up: pcfg_pull_up {
102 #gpio-cells = <2>; 147 bias-pull-up;
148 };
103 149
104 interrupt-controller; 150 pcfg_pull_down: pcfg_pull_down {
105 #interrupt-cells = <2>; 151 bias-pull-down;
106 }; 152 };
107 153
108 gpio1: gpio1@0x2003c000 { 154 pcfg_pull_none: pcfg_pull_none {
109 compatible = "rockchip,gpio-bank"; 155 bias-disable;
110 reg = <0x2003c000 0x100>; 156 };
111 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&cru PCLK_GPIO1>;
113 157
114 gpio-controller; 158 uart0 {
115 #gpio-cells = <2>; 159 uart0_xfer: uart0-xfer {
160 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
161 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
162 };
116 163
117 interrupt-controller; 164 uart0_cts: uart0-cts {
118 #interrupt-cells = <2>; 165 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
119 }; 166 };
120 167
121 gpio2: gpio2@2003e000 { 168 uart0_rts: uart0-rts {
122 compatible = "rockchip,gpio-bank"; 169 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
123 reg = <0x2003e000 0x100>; 170 };
124 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 171 };
125 clocks = <&cru PCLK_GPIO2>;
126 172
127 gpio-controller; 173 uart1 {
128 #gpio-cells = <2>; 174 uart1_xfer: uart1-xfer {
175 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
176 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
177 };
129 178
130 interrupt-controller; 179 uart1_cts: uart1-cts {
131 #interrupt-cells = <2>; 180 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
132 }; 181 };
133 182
134 gpio3: gpio3@20080000 { 183 uart1_rts: uart1-rts {
135 compatible = "rockchip,gpio-bank"; 184 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
136 reg = <0x20080000 0x100>; 185 };
137 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 186 };
138 clocks = <&cru PCLK_GPIO3>;
139 187
140 gpio-controller; 188 uart2 {
141 #gpio-cells = <2>; 189 uart2_xfer: uart2-xfer {
190 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
191 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
192 };
193 /* no rts / cts for uart2 */
194 };
142 195
143 interrupt-controller; 196 uart3 {
144 #interrupt-cells = <2>; 197 uart3_xfer: uart3-xfer {
198 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
199 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
145 }; 200 };
146 201
147 pcfg_pull_up: pcfg_pull_up { 202 uart3_cts: uart3-cts {
148 bias-pull-up; 203 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
149 }; 204 };
150 205
151 pcfg_pull_down: pcfg_pull_down { 206 uart3_rts: uart3-rts {
152 bias-pull-down; 207 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
153 }; 208 };
209 };
154 210
155 pcfg_pull_none: pcfg_pull_none { 211 sd0 {
156 bias-disable; 212 sd0_clk: sd0-clk {
213 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
157 }; 214 };
158 215
159 uart0 { 216 sd0_cmd: sd0-cmd {
160 uart0_xfer: uart0-xfer { 217 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
161 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, 218 };
162 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
163 };
164 219
165 uart0_cts: uart0-cts { 220 sd0_cd: sd0-cd {
166 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; 221 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
167 }; 222 };
168 223
169 uart0_rts: uart0-rts { 224 sd0_wp: sd0-wp {
170 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; 225 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
171 };
172 }; 226 };
173 227
174 uart1 { 228 sd0_pwr: sd0-pwr {
175 uart1_xfer: uart1-xfer { 229 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
176 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, 230 };
177 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
178 };
179 231
180 uart1_cts: uart1-cts { 232 sd0_bus1: sd0-bus-width1 {
181 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; 233 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
182 }; 234 };
183 235
184 uart1_rts: uart1-rts { 236 sd0_bus4: sd0-bus-width4 {
185 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; 237 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
186 }; 238 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
239 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
240 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
187 }; 241 };
242 };
188 243
189 uart2 { 244 sd1 {
190 uart2_xfer: uart2-xfer { 245 sd1_clk: sd1-clk {
191 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, 246 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
192 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
193 };
194 /* no rts / cts for uart2 */
195 }; 247 };
196 248
197 uart3 { 249 sd1_cmd: sd1-cmd {
198 uart3_xfer: uart3-xfer { 250 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
199 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, 251 };
200 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
201 };
202 252
203 uart3_cts: uart3-cts { 253 sd1_cd: sd1-cd {
204 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; 254 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
205 }; 255 };
206 256
207 uart3_rts: uart3-rts { 257 sd1_wp: sd1-wp {
208 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; 258 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
209 };
210 }; 259 };
211 260
212 sd0 { 261 sd1_bus1: sd1-bus-width1 {
213 sd0_clk: sd0-clk { 262 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
214 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
215 };
216
217 sd0_cmd: sd0-cmd {
218 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
219 };
220
221 sd0_cd: sd0-cd {
222 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
223 };
224
225 sd0_wp: sd0-wp {
226 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
227 };
228
229 sd0_pwr: sd0-pwr {
230 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
231 };
232
233 sd0_bus1: sd0-bus-width1 {
234 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
235 };
236
237 sd0_bus4: sd0-bus-width4 {
238 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
239 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
240 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
241 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
242 };
243 }; 263 };
244 264
245 sd1 { 265 sd1_bus4: sd1-bus-width4 {
246 sd1_clk: sd1-clk { 266 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
247 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; 267 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
248 }; 268 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
249 269 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
250 sd1_cmd: sd1-cmd {
251 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
252 };
253
254 sd1_cd: sd1-cd {
255 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
256 };
257
258 sd1_wp: sd1-wp {
259 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
260 };
261
262 sd1_bus1: sd1-bus-width1 {
263 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
264 };
265
266 sd1_bus4: sd1-bus-width4 {
267 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
268 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
269 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
270 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
271 };
272 }; 270 };
273 }; 271 };
274 }; 272 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-06 13:33:00 -0500