diff options
| author | Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> | 2014-10-14 03:01:43 -0400 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-10-29 20:56:28 -0400 |
| commit | 74d89d25f6b0d84f7cd2fc09dc708177787c1465 (patch) | |
| tree | 10e8110f3fd4040c496d335b519b9d139f3abfda /arch/arm/boot/dts/r8a7791.dtsi | |
| parent | 4ba8f2468ce346642b4ace3cdf4bdd8d29175011 (diff) | |
ARM: shmobile: r8a7791: Add MMP clock to device tree
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 98c1b8bef61f..6ce78193985d 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
| @@ -977,18 +977,23 @@ | |||
| 977 | mstp1_clks: mstp1_clks@e6150134 { | 977 | mstp1_clks: mstp1_clks@e6150134 { |
| 978 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 978 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 979 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | 979 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| 980 | clocks = <&m2_clk>, <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | 980 | clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, |
| 981 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; | 981 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
| 982 | <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, | ||
| 983 | <&zs_clk>; | ||
| 982 | #clock-cells = <1>; | 984 | #clock-cells = <1>; |
| 983 | renesas,clock-indices = < | 985 | renesas,clock-indices = < |
| 984 | R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_3DG | 986 | R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU |
| 985 | R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 | 987 | R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG |
| 986 | R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 | 988 | R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 |
| 987 | R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S | 989 | R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 |
| 990 | R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 | ||
| 991 | R8A7791_CLK_VSP1_S | ||
| 988 | >; | 992 | >; |
| 989 | clock-output-names = | 993 | clock-output-names = |
| 990 | "jpu", "tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0", | 994 | "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", |
| 991 | "vsp1-du1", "vsp1-du0", "vsp1-sy"; | 995 | "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", |
| 996 | "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; | ||
| 992 | }; | 997 | }; |
| 993 | mstp2_clks: mstp2_clks@e6150138 { | 998 | mstp2_clks: mstp2_clks@e6150138 { |
| 994 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 999 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |