diff options
author | Phil Edworthy <phil.edworthy@renesas.com> | 2014-06-13 05:37:18 -0400 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2014-06-17 06:58:30 -0400 |
commit | 4bfb37675b5343798f5260adad92a67444a9fd47 (patch) | |
tree | 9aa1340d2bb3d9c984f4ceabf7feb91ce2df0905 /arch/arm/boot/dts/r8a7791.dtsi | |
parent | 745329d280c8c73f00724745693658f3d4113ea8 (diff) |
ARM: shmobile: r8a7791: Add PCIEC clock device tree node
This patch adds the device tree clock node for the PCIe Controller
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
-rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 380d058e4210..a15bf7af63e4 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi | |||
@@ -795,15 +795,16 @@ | |||
795 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 795 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
796 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | 796 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
797 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, | 797 | clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, |
798 | <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; | 798 | <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; |
799 | #clock-cells = <1>; | 799 | #clock-cells = <1>; |
800 | renesas,clock-indices = < | 800 | renesas,clock-indices = < |
801 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 | 801 | R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 |
802 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 | 802 | R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 |
803 | R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 | ||
803 | >; | 804 | >; |
804 | clock-output-names = | 805 | clock-output-names = |
805 | "tpu0", "sdhi2", "sdhi1", "sdhi0", | 806 | "tpu0", "sdhi2", "sdhi1", "sdhi0", |
806 | "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1"; | 807 | "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; |
807 | }; | 808 | }; |
808 | mstp5_clks: mstp5_clks@e6150144 { | 809 | mstp5_clks: mstp5_clks@e6150144 { |
809 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; | 810 | compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |