diff options
author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2014-07-18 19:50:23 -0400 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2014-08-16 20:44:05 -0400 |
commit | c819acdab3bf02795db6d16a17426e21c99c3c28 (patch) | |
tree | 66043d1946c36d62a60fb732e90fe7e9f1c8d9df /arch/arm/boot/dts/r8a7790.dtsi | |
parent | 2cf088105db14c00ad69df09b9b4a37c2370ff44 (diff) |
ARM: shmobile: r8a7790: Add DMAC clocks to DT
Add the SYS-DMAC0 and SYS-DMAC1 clocks to the MSTP2 clock node. They
will be used by the upcoming DMAC DT nodes.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790.dtsi')
-rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index d9ddecbb859c..220662f38435 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi | |||
@@ -758,16 +758,19 @@ | |||
758 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 758 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
759 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | 759 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
760 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | 760 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
761 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; | 761 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, |
762 | <&zs_clk>; | ||
762 | #clock-cells = <1>; | 763 | #clock-cells = <1>; |
763 | renesas,clock-indices = < | 764 | renesas,clock-indices = < |
764 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 | 765 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 |
765 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 | 766 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
766 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 | 767 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 |
768 | R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 | ||
767 | >; | 769 | >; |
768 | clock-output-names = | 770 | clock-output-names = |
769 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", | 771 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
770 | "scifb1", "msiof1", "msiof3", "scifb2"; | 772 | "scifb1", "msiof1", "msiof3", "scifb2", |
773 | "sys-dmac1", "sys-dmac0"; | ||
771 | }; | 774 | }; |
772 | mstp3_clks: mstp3_clks@e615013c { | 775 | mstp3_clks: mstp3_clks@e615013c { |
773 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | 776 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |