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authorStephen Boyd <sboyd@codeaurora.org>2014-01-16 20:25:03 -0500
committerOlof Johansson <olof@lixom.net>2014-01-31 17:58:51 -0500
commit3933d267835c8b0fd2892e2b851f9b2a3991f6c8 (patch)
treef50b1a62b772e3a125cda4599dddabbfdf04456b /arch/arm/boot/dts/qcom-msm8960-cdp.dts
parentde70af494c468c107eedf90090eb74d6ccf30c4c (diff)
ARM: dts: msm: Add clock controller nodes and hook into uart
Add the necessary DT nodes to probe the clock controllers on MSM devices as well as hook up the uart nodes to the clock controllers. This should allow us to boot to a serial console on all DT enabled MSM platforms. Cc: David Brown <davidb@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8960-cdp.dts')
-rw-r--r--arch/arm/boot/dts/qcom-msm8960-cdp.dts18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 6ccbac77931e..7c30de4fa302 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -2,6 +2,8 @@
2 2
3/include/ "skeleton.dtsi" 3/include/ "skeleton.dtsi"
4 4
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6
5/ { 7/ {
6 model = "Qualcomm MSM8960 CDP"; 8 model = "Qualcomm MSM8960 CDP";
7 compatible = "qcom,msm8960-cdp", "qcom,msm8960"; 9 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
@@ -37,11 +39,27 @@
37 reg = <0x800000 0x4000>; 39 reg = <0x800000 0x4000>;
38 }; 40 };
39 41
42 gcc: clock-controller@900000 {
43 compatible = "qcom,gcc-msm8960";
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46 reg = <0x900000 0x4000>;
47 };
48
49 clock-controller@4000000 {
50 compatible = "qcom,mmcc-msm8960";
51 reg = <0x4000000 0x1000>;
52 #clock-cells = <1>;
53 #reset-cells = <1>;
54 };
55
40 serial@16440000 { 56 serial@16440000 {
41 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 57 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
42 reg = <0x16440000 0x1000>, 58 reg = <0x16440000 0x1000>,
43 <0x16400000 0x1000>; 59 <0x16400000 0x1000>;
44 interrupts = <0 154 0x0>; 60 interrupts = <0 154 0x0>;
61 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
62 clock-names = "core", "iface";
45 }; 63 };
46 64
47 qcom,ssbi@500000 { 65 qcom,ssbi@500000 {