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authorLinus Torvalds <torvalds@linux-foundation.org>2013-11-12 01:40:03 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-11-12 01:40:03 -0500
commit8a5dc585d50015af9c079ae2d182dc4c1cd22914 (patch)
tree7544d20587e589bf20c526a5f83205e113cc3e58 /arch/arm/boot/dts/prima2.dtsi
parenteeab517b68beb9e044e869bee18e3bdfa60e5aca (diff)
parent9da8312048edcf246ac1d7ab6aa0293f252de559 (diff)
Merge tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "Main pin control pull request for the v3.13 cycle. The changes hitting arch/blackfin are ACKed by the Blackfin maintainer, and the device tree bindings are ACKed to the extent possible by someone from the device tree maintainers group. - Blackfin ADI pin control driver, we move yet another architecture under this subsystem umbrella. - Incremental updates to the Renesas Super-H PFC pin control driver. New subdriver for the r8a7791 SoC. - Non-linear GPIO ranges from the gpiolib side of things, this enabled simplified device tree bindings by referring entire groups of pins on some pin controller to act as back-end for a certain GPIO-chip driver. - Add the Abilis TB10x pin control driver used on the ARC architecture. Also the corresponding GPIO driver is merged through this tree, so the ARC has full support for pins and GPIOs after this. - Subdrivers for Freescale i.MX1, i.MX27 and i.MX50 pin controller instances. The i.MX1 and i.MX27 is an entirely new family (silicon) of controllers whereas i.MX50 is a variant of the previous supported controller. - Then the usual slew of fixes, cleanups and incremental updates" The ARC DT changes are apparently still pending, that hopefully gets sorted out in a timely manner. * tag 'pinctrl-for-v3.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: imx50: add pinctrl support code for the IMX50 SoC pinctrl: at91: copy define to driver pinctrl: remove minor dead code pinctrl: imx: fix using pin->input_val wrongly pinctrl: imx1: fix return value check in imx1_pinctrl_core_probe() gpio: tb10x: fix return value check in tb10x_gpio_probe() gpio: tb10x: use module_platform_driver to simplify the code pinctrl: imx27: imx27 pincontrol driver pinctrl: imx1 core driver pinctrl: sh-pfc: r8a7791 PFC support sh-pfc: r8a7778: Add CAN pin groups gpio: add TB10x GPIO driver pinctrl: at91: correct a few typos pinctrl: mvebu: remove redundant of_match_ptr pinctrl: tb10x: use module_platform_driver to simplify the code pinctrl: tb10x: fix the error handling in tb10x_pinctrl_probe() pinctrl: add documentation for pinctrl_get_group_pins() pinctrl: rockchip: emulate both edge triggered interrupts pinctrl: rockchip: add rk3188 specifics pinctrl: rockchip: remove redundant check ...
Diffstat (limited to 'arch/arm/boot/dts/prima2.dtsi')
-rw-r--r--arch/arm/boot/dts/prima2.dtsi42
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 7cf78afee7b1..daee58944e15 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -388,6 +388,12 @@
388 sirf,function = "uart0"; 388 sirf,function = "uart0";
389 }; 389 };
390 }; 390 };
391 uart0_noflow_pins_a: uart0@1 {
392 uart {
393 sirf,pins = "uart0_nostreamctrlgrp";
394 sirf,function = "uart0_nostreamctrl";
395 };
396 };
391 uart1_pins_a: uart1@0 { 397 uart1_pins_a: uart1@0 {
392 uart { 398 uart {
393 sirf,pins = "uart1grp"; 399 sirf,pins = "uart1grp";
@@ -526,18 +532,42 @@
526 sirf,function = "usp0"; 532 sirf,function = "usp0";
527 }; 533 };
528 }; 534 };
535 usp0_uart_nostreamctrl_pins_a: usp0@1 {
536 usp0 {
537 sirf,pins =
538 "usp0_uart_nostreamctrl_grp";
539 sirf,function =
540 "usp0_uart_nostreamctrl";
541 };
542 };
529 usp1_pins_a: usp1@0 { 543 usp1_pins_a: usp1@0 {
530 usp1 { 544 usp1 {
531 sirf,pins = "usp1grp"; 545 sirf,pins = "usp1grp";
532 sirf,function = "usp1"; 546 sirf,function = "usp1";
533 }; 547 };
534 }; 548 };
549 usp1_uart_nostreamctrl_pins_a: usp1@1 {
550 usp1 {
551 sirf,pins =
552 "usp1_uart_nostreamctrl_grp";
553 sirf,function =
554 "usp1_uart_nostreamctrl";
555 };
556 };
535 usp2_pins_a: usp2@0 { 557 usp2_pins_a: usp2@0 {
536 usp2 { 558 usp2 {
537 sirf,pins = "usp2grp"; 559 sirf,pins = "usp2grp";
538 sirf,function = "usp2"; 560 sirf,function = "usp2";
539 }; 561 };
540 }; 562 };
563 usp2_uart_nostreamctrl_pins_a: usp2@1 {
564 usp2 {
565 sirf,pins =
566 "usp2_uart_nostreamctrl_grp";
567 sirf,function =
568 "usp2_uart_nostreamctrl";
569 };
570 };
541 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { 571 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
542 usb0_utmi_drvbus { 572 usb0_utmi_drvbus {
543 sirf,pins = "usb0_utmi_drvbusgrp"; 573 sirf,pins = "usb0_utmi_drvbusgrp";
@@ -550,6 +580,18 @@
550 sirf,function = "usb1_utmi_drvbus"; 580 sirf,function = "usb1_utmi_drvbus";
551 }; 581 };
552 }; 582 };
583 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
584 usb1_dp_dn {
585 sirf,pins = "usb1_dp_dngrp";
586 sirf,function = "usb1_dp_dn";
587 };
588 };
589 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
590 uart1_route_io_usb1 {
591 sirf,pins = "uart1_route_io_usb1grp";
592 sirf,function = "uart1_route_io_usb1";
593 };
594 };
553 warm_rst_pins_a: warm_rst@0 { 595 warm_rst_pins_a: warm_rst@0 {
554 warm_rst { 596 warm_rst {
555 sirf,pins = "warm_rstgrp"; 597 sirf,pins = "warm_rstgrp";