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authorTero Kristo <t-kristo@ti.com>2015-02-12 04:35:29 -0500
committerTero Kristo <t-kristo@ti.com>2015-03-31 14:26:58 -0400
commited8509edddebf27e6e69f10c9c314f31ac4f2831 (patch)
tree4adc3f2894383f5234e16e8799dc43b2b3639ce3 /arch/arm/boot/dts/omap5.dtsi
parentefde234674d9db08b762d9faef4dbbaa2eba3a2e (diff)
ARM: dts: omap5: add minimal l4 bus layout with control module support
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
-rw-r--r--arch/arm/boot/dts/omap5.dtsi182
1 files changed, 112 insertions, 70 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..326a429dcce4 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -129,99 +129,141 @@
129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
131 131
132 prm: prm@4ae06000 { 132 l4_cfg: l4@4a000000 {
133 compatible = "ti,omap5-prm"; 133 compatible = "ti,omap5-l4-cfg", "simple-bus";
134 reg = <0x4ae06000 0x3000>; 134 #address-cells = <1>;
135 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 135 #size-cells = <1>;
136 ranges = <0 0x4a000000 0x22a000>;
136 137
137 prm_clocks: clocks { 138 scm_core: scm@2000 {
139 compatible = "ti,omap5-scm-core", "simple-bus";
140 reg = <0x2000 0x1000>;
138 #address-cells = <1>; 141 #address-cells = <1>;
139 #size-cells = <0>; 142 #size-cells = <1>;
143 ranges = <0 0x2000 0x800>;
144
145 scm_conf: scm_conf@0 {
146 compatible = "syscon";
147 reg = <0x0 0x800>;
148 #address-cells = <1>;
149 #size-cells = <1>;
150 };
140 }; 151 };
141 152
142 prm_clockdomains: clockdomains { 153 scm_padconf_core: scm@2800 {
154 compatible = "ti,omap5-scm-padconf-core",
155 "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0 0x2800 0x800>;
159
160 omap5_pmx_core: pinmux@40 {
161 compatible = "ti,omap5-padconf",
162 "pinctrl-single";
163 reg = <0x40 0x01b6>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 #interrupt-cells = <1>;
167 interrupt-controller;
168 pinctrl-single,register-width = <16>;
169 pinctrl-single,function-mask = <0x7fff>;
170 };
171
172 omap5_padconf_global: omap5_padconf_global@5a0 {
173 compatible = "syscon";
174 reg = <0x5a0 0xec>;
175 #address-cells = <1>;
176 #size-cells = <1>;
177
178 pbias_regulator: pbias_regulator {
179 compatible = "ti,pbias-omap";
180 reg = <0x60 0x4>;
181 syscon = <&omap5_padconf_global>;
182 pbias_mmc_reg: pbias_mmc_omap5 {
183 regulator-name = "pbias_mmc_omap5";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <3000000>;
186 };
187 };
188 };
143 }; 189 };
144 };
145 190
146 cm_core_aon: cm_core_aon@4a004000 { 191 cm_core_aon: cm_core_aon@4000 {
147 compatible = "ti,omap5-cm-core-aon"; 192 compatible = "ti,omap5-cm-core-aon";
148 reg = <0x4a004000 0x2000>; 193 reg = <0x4000 0x2000>;
149 194
150 cm_core_aon_clocks: clocks { 195 cm_core_aon_clocks: clocks {
151 #address-cells = <1>; 196 #address-cells = <1>;
152 #size-cells = <0>; 197 #size-cells = <0>;
153 }; 198 };
154 199
155 cm_core_aon_clockdomains: clockdomains { 200 cm_core_aon_clockdomains: clockdomains {
201 };
156 }; 202 };
157 };
158 203
159 scrm: scrm@4ae0a000 { 204 cm_core: cm_core@8000 {
160 compatible = "ti,omap5-scrm"; 205 compatible = "ti,omap5-cm-core";
161 reg = <0x4ae0a000 0x2000>; 206 reg = <0x8000 0x3000>;
162 207
163 scrm_clocks: clocks { 208 cm_core_clocks: clocks {
164 #address-cells = <1>; 209 #address-cells = <1>;
165 #size-cells = <0>; 210 #size-cells = <0>;
166 }; 211 };
167 212
168 scrm_clockdomains: clockdomains { 213 cm_core_clockdomains: clockdomains {
214 };
169 }; 215 };
170 }; 216 };
171 217
172 cm_core: cm_core@4a008000 { 218 l4_wkup: l4@4ae00000 {
173 compatible = "ti,omap5-cm-core"; 219 compatible = "ti,omap5-l4-wkup", "simple-bus";
174 reg = <0x4a008000 0x3000>; 220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0 0x4ae00000 0x2b000>;
175 223
176 cm_core_clocks: clocks { 224 counter32k: counter@4000 {
177 #address-cells = <1>; 225 compatible = "ti,omap-counter32k";
178 #size-cells = <0>; 226 reg = <0x4000 0x40>;
227 ti,hwmods = "counter_32k";
179 }; 228 };
180 229
181 cm_core_clockdomains: clockdomains { 230 prm: prm@6000 {
231 compatible = "ti,omap5-prm";
232 reg = <0x6000 0x3000>;
233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
234
235 prm_clocks: clocks {
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 prm_clockdomains: clockdomains {
241 };
182 }; 242 };
183 };
184 243
185 counter32k: counter@4ae04000 { 244 scrm: scrm@a000 {
186 compatible = "ti,omap-counter32k"; 245 compatible = "ti,omap5-scrm";
187 reg = <0x4ae04000 0x40>; 246 reg = <0xa000 0x2000>;
188 ti,hwmods = "counter_32k";
189 };
190 247
191 omap5_pmx_core: pinmux@4a002840 { 248 scrm_clocks: clocks {
192 compatible = "ti,omap5-padconf", "pinctrl-single"; 249 #address-cells = <1>;
193 reg = <0x4a002840 0x01b6>; 250 #size-cells = <0>;
194 #address-cells = <1>; 251 };
195 #size-cells = <0>;
196 #interrupt-cells = <1>;
197 interrupt-controller;
198 pinctrl-single,register-width = <16>;
199 pinctrl-single,function-mask = <0x7fff>;
200 };
201 omap5_pmx_wkup: pinmux@4ae0c840 {
202 compatible = "ti,omap5-padconf", "pinctrl-single";
203 reg = <0x4ae0c840 0x0038>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 #interrupt-cells = <1>;
207 interrupt-controller;
208 pinctrl-single,register-width = <16>;
209 pinctrl-single,function-mask = <0x7fff>;
210 };
211 252
212 omap5_padconf_global: tisyscon@4a002da0 { 253 scrm_clockdomains: clockdomains {
213 compatible = "syscon"; 254 };
214 reg = <0x4A002da0 0xec>; 255 };
215 };
216 256
217 pbias_regulator: pbias_regulator { 257 omap5_pmx_wkup: pinmux@c840 {
218 compatible = "ti,pbias-omap"; 258 compatible = "ti,omap5-padconf",
219 reg = <0x60 0x4>; 259 "pinctrl-single";
220 syscon = <&omap5_padconf_global>; 260 reg = <0xc840 0x0038>;
221 pbias_mmc_reg: pbias_mmc_omap5 { 261 #address-cells = <1>;
222 regulator-name = "pbias_mmc_omap5"; 262 #size-cells = <0>;
223 regulator-min-microvolt = <1800000>; 263 #interrupt-cells = <1>;
224 regulator-max-microvolt = <3000000>; 264 interrupt-controller;
265 pinctrl-single,register-width = <16>;
266 pinctrl-single,function-mask = <0x7fff>;
225 }; 267 };
226 }; 268 };
227 269