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authorRajendra Nayak <rnayak@ti.com>2013-01-18 09:23:00 -0500
committerBenoit Cousson <benoit.cousson@linaro.org>2013-04-08 18:21:15 -0400
commit1496c15b669c46df412ed1c986864798e4a40a2d (patch)
treec331fa8364984a39e6930d90f4c3a8d72546a942 /arch/arm/boot/dts/omap5.dtsi
parentb45ccc4e4923ad4c9d1b541f52b2b33facd3b0c5 (diff)
ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
Specify both secure as well as nonsecure PPI IRQ for arch timer. This fixes the following errors seen on DT OMAP5 boot.. [ 0.000000] arch_timer: No interrupt available, giving up Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
-rw-r--r--arch/arm/boot/dts/omap5.dtsi5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index aefecf7ca574..71be23997d45 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -41,8 +41,9 @@
41 41
42 timer { 42 timer {
43 compatible = "arm,armv7-timer"; 43 compatible = "arm,armv7-timer";
44 /* 14th PPI IRQ, active low level-sensitive */ 44 /* PPI secure/nonsecure IRQ, active low level-sensitive */
45 interrupts = <1 14 0x308>; 45 interrupts = <1 13 0x308>,
46 <1 14 0x308>;
46 clock-frequency = <6144000>; 47 clock-frequency = <6144000>;
47 }; 48 };
48 49