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authorBenoit Cousson <b-cousson@ti.com>2011-08-16 05:49:08 -0400
committerBenoit Cousson <b-cousson@ti.com>2011-10-04 16:29:40 -0400
commit476b679a5d785d1244f6b43ad26877acf278cd18 (patch)
treec3f93d9742c4654c9d10af829db1122bac0b6f6f /arch/arm/boot/dts/omap3.dtsi
parentad8dfac66fb1995014060302bda19a15bc62bd6d (diff)
arm/dts: OMAP3+: Add mpu, dsp and iva nodes
Add nodes for devices used by PM code (mpu, dsp, iva). Add a cpus node as well as recommended in the DT spec. Remove mpu, dsp, iva devices init if is populated. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3.dtsi')
-rw-r--r--arch/arm/boot/dts/omap3.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d558785c8b2c..d202bb5ec7ef 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,12 +13,31 @@
13/ { 13/ {
14 compatible = "ti,omap3430", "ti,omap3"; 14 compatible = "ti,omap3430", "ti,omap3";
15 15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21
16 /* 22 /*
17 * The soc node represents the soc top level view. It is uses for IPs 23 * The soc node represents the soc top level view. It is uses for IPs
18 * that are not memory mapped in the MPU view or for the MPU itself. 24 * that are not memory mapped in the MPU view or for the MPU itself.
19 */ 25 */
20 soc { 26 soc {
21 compatible = "ti,omap-infra"; 27 compatible = "ti,omap-infra";
28 mpu {
29 compatible = "ti,omap3-mpu";
30 ti,hwmods = "mpu";
31 };
32
33 iva {
34 compatible = "ti,iva2.2";
35 ti,hwmods = "iva";
36
37 dsp {
38 compatible = "ti,omap3-c64";
39 };
40 };
22 }; 41 };
23 42
24 /* 43 /*