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authorFlorian Vaussard <florian.vaussard@epfl.ch>2014-03-07 14:22:15 -0500
committerTony Lindgren <tony@atomide.com>2014-03-12 13:17:27 -0400
commitdd4051bd2daaeedfd1bff32ee2ee6f4107b2257a (patch)
treec851ed82a0c0b898e184bf552f35a8d0c92f0cc4 /arch/arm/boot/dts/omap3-overo-base.dtsi
parent94647a30124e2c7243ffcd780862ed591ae36450 (diff)
ARM: dts: omap3-overo: Add HSUSB PHY
Add the High-Speed USB PHY. Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap3-overo-base.dtsi')
-rw-r--r--arch/arm/boot/dts/omap3-overo-base.dtsi44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi
index edac70e9204c..13d1ad215494 100644
--- a/arch/arm/boot/dts/omap3-overo-base.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-base.dtsi
@@ -30,6 +30,24 @@
30 ti,codec = <&twl_audio>; 30 ti,codec = <&twl_audio>;
31 }; 31 };
32 32
33 /* HS USB Port 2 Power */
34 hsusb2_power: hsusb2_power_reg {
35 compatible = "regulator-fixed";
36 regulator-name = "hsusb2_vbus";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 gpio = <&gpio6 8 0>; /* gpio_168: vbus enable */
40 startup-delay-us = <70000>;
41 enable-active-high;
42 };
43
44 /* HS USB Host PHY on PORT 2 */
45 hsusb2_phy: hsusb2_phy {
46 compatible = "usb-nop-xceiv";
47 reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */
48 vcc-supply = <&hsusb2_power>;
49 };
50
33 /* Regulator to trigger the nPoweron signal of the Wifi module */ 51 /* Regulator to trigger the nPoweron signal of the Wifi module */
34 w3cbw003c_npoweron: regulator-w3cbw003c-npoweron { 52 w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
35 compatible = "regulator-fixed"; 53 compatible = "regulator-fixed";
@@ -64,6 +82,11 @@
64}; 82};
65 83
66&omap3_pmx_core { 84&omap3_pmx_core {
85 pinctrl-names = "default";
86 pinctrl-0 = <
87 &hsusb2_pins
88 >;
89
67 uart2_pins: pinmux_uart2_pins { 90 uart2_pins: pinmux_uart2_pins {
68 pinctrl-single,pins = < 91 pinctrl-single,pins = <
69 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ 92 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
@@ -116,6 +139,19 @@
116 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ 139 OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
117 >; 140 >;
118 }; 141 };
142
143 hsusb2_pins: pinmux_hsusb2_pins {
144 pinctrl-single,pins = <
145 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
146 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
147 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
148 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
149 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
150 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
151 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
152 OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */
153 >;
154 };
119}; 155};
120 156
121&i2c1 { 157&i2c1 {
@@ -177,6 +213,14 @@
177 power = <50>; 213 power = <50>;
178}; 214};
179 215
216&usbhshost {
217 port2-mode = "ehci-phy";
218};
219
220&usbhsehci {
221 phys = <0 &hsusb2_phy>;
222};
223
180&uart2 { 224&uart2 {
181 pinctrl-names = "default"; 225 pinctrl-names = "default";
182 pinctrl-0 = <&uart2_pins>; 226 pinctrl-0 = <&uart2_pins>;